Thermally stimulated currents (TSCs) have been measured to investigate electron traps in HfO2 prepared by reactive sputtering on silicon. Broken planes of the silicon crystal, which may contribute to the occurrence of interface states, were identified between the silicon and SiOx interlayer by transmission electron microscopy (TEM). A second domain was found between SiOx and HfO2 constituting a gradual transition region between the two oxides. This interface region was found to be a source of unstable charge traps where captured electrons interact with the silicon energy states through a combined tunneling and thermal process.

Thermally stimulated currents (TSCs) have been measured to investigate electron traps in HfO2 prepared by reactive sputtering on silicon. Broken planes of the silicon crystal, which may contribute to the occurrence of interface states, were identified between the silicon and SiOx interlayer by transmission electron microscopy (TEM). A second domain was found between SiOx and HfO2 constituting a gradual transition region between the two oxides. This interface region was found to be a source of unstable charge traps where captured electrons interact with the silicon energy states through a combined tunneling and thermal process. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3530845] All rights reserved.

The mechanisms determining emission of holes in self-assembled Ge quantum dots (QDs) embedded in the p-type Si matrix have been investigated. Specimens were prepared by molecular beam epitaxy (MBE). Electrical methods such as deep level transient spectroscopy (DLTS) and capacitance versus voltage (C-V) measurements were used for the study. The emission mechanisms were identified by measuring a QD-related signal as a function of the repetition frequency of the filling pulses with the reverse voltage and the pulse voltage as a parameter. An observed shift of the signal position or its absence versus the voltage parameters was interpreted in terms of thermal, tunnelling and mixed processes and attributed to the presence of a Coulomb barrier formed as a result of the charging effect. Thermal emission properties of the QDs were characterized under such measurement conditions that tunnelling contributions to the DLTS spectra could be neglected. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Ge quantum well (QW) structures were prepared through Si-capping of 3.3 ML of Ge by MBE on p(+)-(001) Si substrates at a growth temperature of 550 degrees C. The spatial variation of hole eigen energies in the QW were revealed by DLTS. Depending on the position on the wafer surface, the hole emission may be imposed by a lateral quantum confinement effect. Results of a study by HRTEM methods demonstrate pronounced fluctuations of the QW thickness and variations of the strain field in the QW.

Admittance spectroscopy is extended for measuring capacitance and conductance on metal-oxide-semiconductor (MOS) structures as a function of gate voltage, frequency, and temperature. An automatic setup has been designed for collecting data along these dimensions in one measurement cycle. The theory for admittance spectroscopy has been developed by starting from basic charge carrier statistics. Using numerical integration of energy dependent parameters instead of the commonly used analytical solution, conductance dispersion curves are obtained which do not need to be adjusted by assuming lateral surface potential variations at the oxide-semiconductor interface. Also, we find that interface state densities extracted by using traditional methods are four times lower than those obtained by using our theory. Experimental data presented in three-dimensional plots are compared with theoretical calculations, revealing the possibilities and limitations of the conductance method.

We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd"2O"3) from a silicon oxide (SiO"2) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).

Starting from basic statistical properties of interface states, we demonstrate the influence of energy dependent interface state distributions and thermal emission rates including their capture cross sections on measured differential conductance data for Al/HfO2/SiOx/Si structures. Theoretical plots calculated this way reproduce experimental conductance data without correction for lateral surface potential variations. Close to the silicon conduction band edge, we find an energy dependence of the capture cross sections revealing the existence of electron states with capture processes deviating from the multiphonon mechanisms found for the deeper lying states at interfaces between high-k dielectrics and silicon.

The authors report on the investigation of amorphous Gd-based silicates as high-k dielectrics. Two different stacks of amorphous gadolinium oxide (Gd2O3) and silicon oxide (SiO2) on silicon substrates are compared after annealing at temperatures up to 1000°C. Subsequently formed metal oxide semiconductor capacitors show a significant reduction in the capacitance equivalent thicknesses after annealing. Transmission electron microscopy, medium energy ion scattering, and x-ray diffraction analysis reveal distinct structural changes such as consumption of the SiO2 layer and formation of amorphous Gd silicate. The controlled formation of Gd silicates in this work indicates a route toward high-k dielectrics compatible with conventional, gate first complementary metal-oxide semiconductor integration schemes.

For nanowires with Schottky barriers on the end surfaces, charges on the walls of the wire are close enough to the metal–semiconductor interface to influence the Schottky barrier. This is similar to an effect in planar structures, where impurities with energy levels below the Fermi level in the bulk of the substrate material will change charge state in the depletion region of a metal–semiconductor structure if the Schottky barrier is high enough to bring the impurity energy level above the Fermi level. The mechanism for barrier modulation is the same in both cases and occurs in nanowires as a result of the wire geometry.

Due to the geometry offered by nanowires, it is possible to introduce electric fields directed from the wire wall toward a Schottky contact positioned on the end surface of a wire. In the present work a simple model demonstrating the effect of charge on the wire walls close to the metal semiconductor interface is presented. This is also compared to measurements on fabricated nanowire devices, showing that additional positive charge close to the interface will lower the effective Schottky barrier height.

In this work, we present experimental results examining the energy distribution of the relatively high (>1×10^11 cm−2) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal–insulator–silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H2/N2 annealing following the gate stack formation, reveals a peak density (~2×10^12 cm−2 eV−1 to ~1×10^13 cm−2 eV−1) at 0.83–0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si(100). The characteristic peak in the interface state density (0.83–0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (Pbo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H2/N2) annealing over the temperature range 350–555°C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed.

Electron traps in HfO 2 have been investigated by measuring thermally stimulated current (TSC). Two different interface regions have been identified where captured electrons interact with energy band states. The two domains are separated by and close to the ldquointerlayerrdquo of SiO x commonly present in high-k/silicon stacks. On the inner side, between SiO x and silicon, we find an irregular silicon crystal which we interpret as a source for interface states. At the SiO x /HfO 2 interface, we find a high concentration of unstable traps with a strong influence on the electric field distribution in the gate stack.

In this work, we present experimental results examining the energy distribution of the relatively high (> 1 X 10(11) cm(-2)) electrically active interface defects which are commonly observed in high-dielectric-constant (high-k) metal-insulator-silicon systems during high-k process development. This paper extends previous studies on the Si(100)/SiOx/HfO2 system to include a comparative analysis of the density and energy distribution of interface defects for HfO2, lanthanum silicate (LaSiOx), and Gd2O3 thin films on (100) orientation silicon formed by a range of deposition techniques. The analysis of the interface defect density across the energy gap, for samples which experience no H-2/N-2 annealing following the gate stack formation, reveals a peak density (similar to 2 X 10(12) cm(-2) eV(-1) to similar to 1 X 10(13) cm(-2) eV(-1)) at 0.83-0.92 eV above the silicon valence bandedge for the HfO2, LaSiOx, and Gd2O3 thin films on Si (100). The characteristic peak in the interface state density (0.83-0.92 eV) is obtained for samples where no interface silicon oxide layer is observed from transmission electron microscopy. Analysis suggests silicon dangling bond (P-bo) centers as the common origin for the dominant interface defects for the various Si(100)/SiOx/high-k/metal gate systems. The results of forming gas (H-2/N-2) annealing over the temperature range 350-555 degrees C are presented and indicate interface state density reduction, as expected for silicon dangling bond centers. The technological relevance of the results is discussed. (c) 2007 The Electrochemical Society.

Using a method based on the frequency dependence of capacitance, cross sections for electron capture into energy states at the interlayer/silicon interface have been investigated for HfO2 that is deposited on silicon by reactive sputtering. We find that the capture cross sections are thermally activated and steeply increase with increasing energy depth. Both features can be attributed to the same physical origin, indicating vibronic trap properties, where the capture mechanism is governed by multiphonon processes.

Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 prepared by MBE and ALD, and for HfO2 prepared by reactive sputtering, by measuring the frequency dependence of MOS capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.