A procedure is described that assures the reliable operation in space radiation environments of memory systems that are approximately ten times larger and can be built at about one tenth of the cost of recent, comparable satellite projects. The procedure accounts for combined radiation effects, permitting the radiation tolerance of the memory system to be accurately estimated. Using the procedure a 1-gigabit memory with error detection and correction capability has been designed for a miniature satellite applications. The memory system is constructed entirely out of commercial grade microelectronics

Factors that influence the fidelity of gamma-ray TREE testing are investigated. Specifically, package-induced dose enhancement in 256K CMOS static-random-access-memories (SRAMs) and dose enhancement from finite-range electrons produced (by gamma-ray interactions) in materials external to the SRAM packages are studied. Two gamma-ray simulators with significantly different spectra are used in the st...

Radiation-induced upset levels in SA3001 static random access memories (SRAMs) and SA3246 clock integrated circuits (ICs) have been measured in a medium-energy flash X-ray environment (average photon energy approximately 100 keV), where dose-enhancing effects are very important. By comparing device responses using a non-dose-enhancing ceramic package lid and a dose-enhancing Kovar/gold lid, dose-enhancement factors for photocurrent and upset were generated. The observed upset enhancement factors of 3.0+or-0.5 (SRAM) and 2.2+or-0.2 (clock IC) are in excellent agreement with measurements of photocurrent enhancement factors (2.5+or-0.5) in diodes processed with the same diffusions as the complementary metal-oxide-semiconductor (CMOS) ICs irradiated in a steady-state X-ray environment. These results indicate that upset is dominated by the radiation-induced transient supply current in these ICs, and that steady-state diode photocurrent measurements are a good predictor of both photocurrent and upset enhancement for ICs made with this technology. >

Radiation-hardened MOS ICs and transistors were irradiated using several high-dose-rate sources. A strong dependence of the dose-to-failure level is observed for different circuit designs, the dose per pulse, package temperature, and the average dose rate of the radiation source at ambient and elevated temperatures. The results indicate that extrapolating very high dose rate IC and transistor prop...

Cumulative fractions for linear energy transfer spectra were measured for particles ejected from microelectronics packaging materials subjected to neutron and proton irradiations. The measurements for the neutron irradiations compare well with Monte Carlo theoretical calculations. The spectra can be used to access microelectronics vulnerabilities in strategic-nuclear-weapon, space-trapped, and neu...

The single-event-upset (SEU) characteristics of a CMOS SRAM cell irradiated under conditions that simulate the total-dose degradation anticipated in space applications were experimentally and theoretically investigated. Simulations of SEU sensitivity utilizing a 2-D circuit/device simulator, with measured transistor threshold-voltage shifts and mobility degradations as inputs, are shown to be in g...

Time constants for voltage transients following high energy ion strikes on static memories are determined from a series of experiments measuring cross sections for single-event upset. For a given strike location within the circuit, the transient time constant saturates with increasing deposited energy. These maximum transients, for strikes at the two known sensitive areas, 'off' p-channel drain an...

We report theoretical calculations and experimental verification of an increase in memory cell SEU tolerance when Sandia's 2μm-technology 16K SRAMs are fabricated with a radiation-hardened 1-μm CMOS process. An advanced 2D transient transport-plus-circuit simulator has been employed to calculate the differential contributions from each of the vertical dimensional changes in the transition from the...

In this paper the problem of determining a piece-part test program based on system reliability objectives is considered. In particular we show how conventional single-sample plans can be extended to include a demonstration of system reliability by numerical simulation of system tests. A theoretical basis for test planning is suggested which may be of use to both producers and consumers of radiation hardened piece parts.

A new single event upset (SEU) hardening concept, an LRAM cell, is demonstrated theoretically and experimentally. Decoupling resistors in the LRAM are used only to protect against the short n-channel transient; longer persisting pulses are reduced in magnitude by a voltage divider, a basically new concept for SEU protection. In such a design, smaller resistors provide SEU tolerance, allowing higher performance, hardened memories. As basis for the LRAM idea, techniques were developed to measure time constants for ion induced voltage transients in conventional static random access memories, SRAM. Time constants of 0.8 and 6.3 nsec were measured for transients following strikes at the n- and p-channel drains, respectively--primary areas of SEU sensitivity. These data are the first transient time measurements on full memory chips and the large difference is fundamental to the LRAM concept. Test structures of the new design exhibit equivalent SEU tolerance with resistors 5-to-10 times smaller than currently used in SRAM. Our advanced transport-plus-circuit numerical simulations of the SEU process predicted this result and account for the LRAM experiments, as well as a variety of experiments on conventional SRAM.

The authors observed that neutron-induced fission of uranium contaminants present in alumina ceramic package lids results in the release of fission fragments that can cause hard errors in metal-nitride-oxide nonvolatile RAMs (MNOS NVRAMs). Hard error generation requires the simultaneous presence of (1) a fission fragment with a linear energy transfer (LET) greater than 20 MeV/mg/cm/sup **2/ moving at an angle of 30 degrees or less from the electric field in the high-field, gate region of the memory transistor, and (2) a WRITE or ERASE voltage on the oxide-nitride transistor gate. In reactor experiments, they observe these hard errors when a ceramic lid is used on both MNOS NVRAMs and polysilicon-nitride-oxide (SNOS) capacitors, but hard errors are not observed when a gold-plated kovar lid is used on the package containing these die. They mapped the tracks of the fission fragments released from the ceramic lids with a mica track detector and used a Monte Carlo model of fission fragment transport through the ceramic lid to measure the concentration of uranium present in the lids. The authors' concentration measurements are in excellent agreement with other's measurement of uranium concentration in ceramic lids. The authors' Monte Carlo analyses also agree closely with theirmore » measurements of hard error probability in MNOS NVRAMs.« less

The dependence of SEU hardness on the scale of circuit integration in memories has been investigated experimentally and theoretically. Numerical simulations are used to separate effects of doping levels and vertical dimensions, which generally harden the cell with increasing integration, from effects of lateral dimension shrinkage, that have the opposite effect. These calculations are compared to SEU data from memories that were either (1) fabricated at Sandia using the CMOS-III 2..mu.. process or (2) fabricated at AT and T using identical lateral dimensions, but with processes characteristic of the AT and T 1..mu.. technology, i.e., different vertical dimensions and doping levels.