To unlock the full performance potential of silicon heterojunction solar cells requires reductions of parasitic absorption and shadowing losses. Yet the translation of the hydrogenated nanocrystalline silicon oxide (nc-SiOx:H) window layer and copper-plated electrodes to a cost-effective and scalable production-relevant context remains one of the largest roadblocks towards mainstream adoption of silicon heterojunction technology. Here we address the first challenge by developing an industrial-scale high-frequency plasma-enhanced chemical vapour deposition system with a minimized standing wave effect, enabling the deposition of doped nc-SiOx:H with excellent electron selectivity, low parasitic absorption and high uniformity. Next, we demonstrate seed-free copper plating, resulting in grids with a high aspect ratio and low metal fraction. By implementing the doped nc-SiOx:H window layer, certified efficiencies of 25.98% and 26.41% are obtained for M6-size bifacial silicon heterojunction devices with screen-printed silver electrodes and copper-plated electrodes, respectively. These results underline the performance potential of silicon heterojunction technology and lower the threshold towards their mass manufacturing. By tuning the plasma frequency, Yu, Gao et al. develop an industrial-scale chemical vapour deposition system for uniform nanocrystalline silicon oxide coatings, enabling 26.41% efficiency in silicon heterojunction solar cells with copper electrodes.

Copper-plated interconnects were widely adopted for volume manufacture of integrated circuits after more than a decade of intensive research to demonstrate that use of Cu would not impact device reliability. However, although Cu-plated metallisation promises significantly reduced costs for Si photovoltaics, its adoption in manufacturing has not gained the same traction. This review identifies some key challenges facing the introduction of Cu-plated metallisation for Si photovoltaics. These include the following: (1) increased carrier recombination due to the use of Cu for metal contact formation; (2) reduced module reliability due to adhesion or contact integrity failures; and (3) limited availability of cost-effective processes and equipment for metal plating. For integrated circuits, Cu's low electrical resistance and high resistance to electromigration provided an impetus for the large investment in process development that was required to realise Cu-plated interconnects. However, the technical advantages of using Cu for Si solar cell contacts are not as compelling, as solar cells can tolerate larger feature sizes thus reducing the criticality of the contact metal's conductivity and electromigration properties. Additionally, for Si photovoltaics, low cost is paramount, and new challenges arise from the need for modules to absorb light and operate in the field for 25+ years in diverse outdoor climates. However, with the scale of Si photovoltaic manufacturing expected to increase dramatically in the next decade, the use of large quantities of silver for cell metallisation will provide an incentive to address reliability concerns regarding the use of Cu for Si photovoltaic metallisation.

This work demonstrates the first application of LA-ICP-MS for detection of substrate contamination from plated metals in silicon solar cells.

This paper reports on the observed diffusion of plated copper through silver capping layers during thermal stability testing of copper-plated silicon solar cells. Distortion of Suns-V OC curves was observed on plated solar cells after extended thermal exposure at 200 °C for 500 hrs, reducing the accuracy of Arrhenius analyses of long-term stability. Cross-sectional imaging revealed the source of the distortion to be high contact resistance due to void formation between the bulk copper and the silver capping layer in the contact stack, the voids occurring as a result of copper diffusing through the capping metal. The extent of void formation was shown to be dependent on the microstructure of the capping layer, highlighting the limitations of using plated metals as diffusion barriers.

Application of 266-nm picosecond (ps) laser ablation and copper (Cu)-plated metallization to p-type selective emitter (SE) passivated emitter and rear cells (PERC) is reported in this paper. Use of a 266-nm ps laser resulted in similar laser-induced periodic surface structures as observed for 355-nm ps laser ablation of a silicon (Si) nitride antireflection coating (ARC) on random-textured Si solar cell surfaces. In addition, it is shown that 266-nm ps laser ablation results in the formation of amorphous Si with an underlying distorted crystalline Si layer at the laser-ablated surfaces. The successful alignment of laser-ablated openings to the heavily doped SE regions resulted in a comparable cell efficiency of Cu-plated SE PERC cells to screen-printed controls, with a maximum cell efficiency of 20.6% being achieved for the Cu-plated cells. The plated cell performance was limited by the recombination losses, and in particular nonideal recombination caused by the use of a shallow emitter, which had been optimized for screen-printed metallization. Engineering of an SE with a junction depth of 0.52 mu m in the heavily doped regions resulted in a 0.3% absolute increase in pseudo fill factor and demonstrated the importance of displacing the p-n junction from the laser-ablated Si surface. Although 355-nm ps laser ablation has been demonstrated to result in strong busbar adhesion in previous reports of Cu-plated cells, significant variability in the busbar adhesion of the fully plated SE PERC cells resulted by 266-nm ps laser ablation. The predicted increased sensitivity of 266-nm laser ablation to the ARC thickness and the possibility that surface oxides were not uniformly removed across wafers before plating may have affected the uniformity of silicide formation and hence the adhesion of the plated busbars.

While it is well known that copper impurities can be relatively easily gettered from the silicon bulk to the phosphorus or boron–doped surface layers, it has remained unclear how thermally stable the gettering actually is. In this work, we show experimentally that a typical rapid thermal anneal (RTA, a few seconds at 800 °C) used commonly in the semiconductor and photovoltaic industries is sufficient to release a significant amount of Cu species from the phosphorus-doped layer to the wafer bulk. This is enough to activate the so-called copper-related light-induced degradation (Cu-LID) which results in significant minority carrier lifetime degradation. We also show that the occurrence of Cu-LID in the wafer bulk can be eliminated both by reducing the RTA peak temperature from 800 °C to 550 °C and by slowing the following cooling rate from 40–60 °C/s to 4 °C/min. The behavior is similar to what is reported for Light and Elevated Temperature degradation, indicating that the role of Cu cannot be ignored when studying other LID phenomena. Numeric simulations describing the phosphorus diffusion and the gettering process reproduce the experimental trends and elucidate the underlying physical mechanisms.

In this work, we develop a fabrication process for an interdigitated back contact solar cell using BBr3 diffusion to form the p+ region and POCl3 diffusion to form the n+ regions. We use the industry standard technology computer‐aided design modelling package, Synopsys Sentaurus, to optimize the geometry of the device using doping profiles derived from electrochemical capacitance voltage measurements. Cells are fabricated using n‐type float‐zone silicon substrates with an emitter fraction of 60%, with localized back surface field and contact holes. Key factors affecting cell performance are identified including the impact of e‐beam evaporation, dry etch damage, and bulk defects in the float zone silicon substrate. It is shown that a preoxidation treatment of the wafer can lead to a 2 ms improvement in bulk minority carrier lifetime at the cell level, resulting in a 4% absolute efficiency boost.

Shielded hydrogen passivation (SHP) is a recently developed technique for introducing atomic hydrogen into materials and it offers significant advantages over the other hydrogenation techniques. Hydrogen de‐activation of boron followed by electrochemical CV profiling was used to demonstrate that substantial quantities of atomic hydrogen can permeate though palladium/silver alloy foils which are 10 µm thick. It is thought that such thickness will be sufficient to withstand pressures of up to 1 atmosphere allowing passivation in an in‐line process. Further, it is shown that poisoning of the foil by using sulphur increases the flux of atomic hydrogen released. SHP delivers extremely good passivation of SiO 2 ‐Si interfaces, as demonstrated by using thermally oxidised 1 Ω‐cm, n‐type silicon where the lifetime, at 10 15 cm −3 injection level, was found to increase from 12 to 1.05 ms after SHP processing. Upon application of corona charge, the lifetime further increased to 6.3 ms, equivalent to SRV ≤ 0.17 cm s −1 .

In this study, silicon solar cells with copper-plated front side metallisation were exposed to long-term reliability thermal stress conditions and the material integrity of the plated contacts after stress testing was investigated using imaging and electrical measurements. Significant voltage ‘bend-back’ was observed in Suns-VOC measurements at high illumination intensities (> 1Sun) following thermal stress testing at 200°C for 500h of laser-ablated cells with a nickel/copper/silver plated front metal grid. Using a combination of focussed ion beam milling, high resolution imaging and energy dispersive X-ray spectroscopy, it was shown that large voids can form between the silver capping layer and the main copper stack during thermal annealing. However, even more revealing was the detection of a new metal layer comprising largely of diffused copper overlying the silver capping. The cause of the Schottky ‘bend-back’ behaviour was theorised to be due to increased contact resistance arising from the voids which are presumed to form as a result of grain boundary diffusion of copper through the silver capping layer. Errors of 5–10% in the determination of pFF from Suns-VOC occur as a result, with the scale of the error dependent on the capping method and sintering conditions. Collapsing the voids was subsequently shown to remove the Schottky behaviour and improve reliability of the fitted diode parameters extracted from Suns-VOC measurements.

Light-induced plating presents a potentially lower-cost alternative to screen-printed Ag for silicon solar cell metallization. This paper presents results of experiments that investigated the effects of bias current density and post-plating rapid thermal processing (RTP) on plated Cu finger microstructure and texture. It is shown that the Cu, if not annealed after plating, self-anneals with time resulting in grain growth and increased (200) to (111) grain texture which is associated with increased tensile stress. The rate of self-annealing is much faster with high plating current densities. Post-plating RTP annealing enables fast annealing and stable Cu fingers with a low ratio of (200) to (111) grain texture. These findings have important implications for plated finger adhesion and highlight the importance of annealing after plating for reliable Cu plated metallization.

Light-induced plating (LIP) presents a potentially lower-cost alternative to screen-printed silver (Ag) for front surface silicon solar cell metallization. This paper presents the results of experiments that investigated the effects of bias current density, post-plating rapid thermal processing (RTP) and electrolyte chemistry on plated copper (Cu) finger microstructure, crystal texture and resistance. It is shown that the Cu fingers, if not rapidly annealed immediately after plating, self-anneal resulting in grain growth and an increased (200) to (111) grain texture ratio which is indicative of increased tensile stress in the Cu fingers. The resistance in the fingers also decreases due to reduced scattering arising from the fewer and larger grains formed during self-annealing. The rate of self-annealing is faster with higher plating current densities and can vary for different plating electrolytes, presumably due to differing levels and types of incorporated impurities. The changes in plated Cu microstructure due to self-annealing may impact electrical reliability and adhesion of metal contacts plated using LIP for silicon solar cells where the grid geometry requirements may cause differences in the plating rate and hence self-annealing rate across a cell. Use of an RTP after Cu plating can reduce this variability with a lower and stable ratio of (200) to (111) grain texture resulting after thermal annealing, however voids can form near grain boundaries in thermally-annealed Cu fingers as they cool. (C) 2016 The Electrochemical Society. All rights reserved.

We report fabrication of nanostructured, laser-doped selective emitter (LDSE) silicon solar cells with power conversion efficiency of 18.1% and a fill factor (FF) of 80.1%. The nanostructured solar cells were realized through a single step, mask-less, scalable reactive ion etch (RIE) texturing of the surface. The selective emitter was formed by means of laser doping using a continuous wave (CW) laser and subsequent contact formation using light-induced plating of Ni and Cu. The combination of RIE-texturing and a LDSE cell design has to our knowledge not been demonstrated previously. The resulting efficiency indicates a promising potential, especially considering that the cell reported in this work is the first proof-of-concept and that the fabricated cell is not fully optimized in terms of plating, emitter sheet resistance and surface passivation. Due to the scalable nature and simplicity of RIE-texturing as well as the LDSE process, we consider this specific combination a promising candidate for a cost-efficient process for future Si solar cells.

Light-induced plating (LIP)of Ni/Cu presents a potentially lower-cost alternative to screen-printed Ag for silicon solar cell metallization. This paper presents results of self-annealing and post-plating rapid thermal processing (RTP) of plated Cu finger microstructure, texture and resistance. It is shown that the plated Cu conductors, if not thermally-annealed immediately after plating, self-anneal with time resulting in grain growth and increased (200) to (111) grain texture which occurs with increased tensile stress. Post-plating RTP annealing enables fast annealing and stable Cu fingers with a low ratio of (200) to (111) grain texture. These findings have important implications for plated finger adhesion and highlight the importance of annealing after plating for reliable Cu plated metallization.

This paper reports on an investigation into the use of laser ablation inductively-coupled plasma mass spectrometry (LA-ICPMS) in analyzing copper diffusion through nickel barrier layers in selective-emitter silicon solar cells. Cells plated with nickel and copper were heat-treated at 200 °C for up to 15 hours. Following quenching in ethylene glycol, significant degradation was observed in the plated cells, whereas no degradation was observed in the slow cooled cells. Impurity analysis with high spatial resolution was obtained with LA-ICPMS, showing higher copper content in copper-plated cells after heat treatment compared to cells without copper plating or heat treatment. The limitations of LA-ICPMS for quantitative analysis and the importance of minimizing surface contamination to improve technique sensitivity are also highlighted.