In this study, organic memory devices with a single active layer between the two external electrodes were fabricated using an electron-donor type conjugated polymer and an electron-acceptor type small organic molecule. The active layer of the memory device was prepared by blending polystyrene, poly[10-(2'-ethylhexyl)phenothiazine-3,7-diyl], and tetracyanoquinodimethane in 1,2-dichlorobenzene. The device initially showed a low-conductance state (OFF state) in the low-voltage range, and an abrupt current increase, corresponding to the transition to a high-conductance state (ON state), occurred at a certain voltage (V-th). The ON state could be reverted to the OFF state by applying a voltage higher than V-th. The current ratio between the two states was about 10(3) (up to 10(5)). After this transition, the device remained in the ON state even after the applied voltage was removed, and this indicated the nonvolatile characteristics of the device. There was no sharp current degradation in the OFF or ON states for 4500 s of continuous bias. The device-to-device performance fluctuation was measured, and the conduction mechanisms in the ON and OFF states were examined by fitting the data to well-known theoretical models. (C) 2012 Wiley Periodicals, Inc. J Polym Sci Part A: Polym Chem 50: 2188-2193, 2012

We report a flexible photoresponsive organic field-effect transistor, phototransistor (OPT), based on a fluorinated copperphthalocyanine (F16CuPc) and polymer gate dielectric on a flexible polyimide substrate. Under light illumination, the device exhibited a photoresponsivity of 2.15 mA/W at VGS = 2 V and optical power of 5.66 mW/cm2. The current ratio (Iphoto/Idark) of the light to dark states was calculated to be around 300 at VGS = 2 V. Furthermore, the switching time of the phototransistor was found to be lower than 0.1 s. When the substrate was bent outward up to a bending radius of 4.4 mm, the device still showed photoresponsive field-effect characteristics. However, the photoresponsivity and Iphoto/Idark ratio decreased with decreasing bending radius. These results indicate that the present flexible OPT could potentially be used in optoelectronic device applications.

Transistor mismatch data and analysis from poly/SiON and high-k/metal-gate (HKMG) bulk CMOS technologies are presented. It is found that the traditional mismatch figure of merit from the Pelgrom plot (AVT) continuously scales down as technology advances. Furthermore, the AVT values for both nFET and pFET in the HKMG technology are significantly reduced from poly/SiON technologies. By normalizing t...

The one-dimensional nano/microstructures of metal-organic complex (Ag-TCNQ) were synthesized by solution route via the reaction between Ag film and TCNQ. We have grown micrometer-sized Ag-TCNQ crystals by simply spin-coating the TCNQ solution over Ag substrate and treating at elevated temperature. The reproducible memory behavior with on/off ratio ∼500 has been observed in devices based on Ag-TCNQ nano/microcrystals. The on/off ratio of the devices has been increased by more than 2 orders of magnitude by incorporating a layer of polymer on top of the TCNQ film. The mass production of large size crystals via this method holds great promise for applications in high-density information storage.

Gate-induced-drain-leakage (GIDL) current in 45-nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2-V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling of electrons through the reverse-biased channel-to-drain p-n junction. A band-to-band tunneling model is used to fit the measured GIDL currents under different channel-doping levels and bias conditions. Good agreement is obtained between the modeled results and experimental data. In addition, the dependence of the GIDL current on body bias, lateral electric field, channel width, and temperature is characterized and discussed.

We report the fabrication of pentacene organic field-effect transistors (OFETs) using a fluorinated styrene-alt-maleic anhydride copolymer gate dielectric, which was prepared from styrene derivatives with a fluorinated side chain [-CH 2 -O-(CH 2 ) 2 -(CF 2 ) 5 CF 3 ] and maleic anhydride through a solution polymerization technique. The fluorinated side chain was used to impart hydrophobicity to the surface of the gate dielectric and maleic anhydride was employed to improve its wetting properties. A field-effect mobility of 0.12 cm 2 /Vs was obtained from the as-prepared top-contact pentacene FETs. Since various functional groups can be introduced into the copolymer due to the nature of maleic anhydride, its physical properties can be manipulated easily. Using this type of copolymer, the performance of organic FETs can be enhanced through optimization of the interfacial properties between the gate dielectric and organic semiconductor.

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (IPEAK) is a key parameter. Ieff is commonly defined as the average between IH and IL, where IH=Ids(Vgs=VDD, Vds=0.5VDD) and IL = Ids(Vgs=0.5VDD, Vds=VDD). In the past, this Ieff definition has been accurate in modeling the inverter delay. However, we find that as devices are scaled further into the nanoscale regime, the maximum transient current can deviate severely from IH, in which case, another metric should be used. The deviation of IPEAK from IH is found to increase as delay decreases or as device overdrive voltage increases. We define Ieff = (IPEAK+IM+IL)/ 3, where IM = Ids(Vgs=0.75VDD, Vds=0.75VDD). We evaluate our model against others by comparing the analytical and HSPICE extracted Ieff ratios across devices of varying threshold voltages, VTH. Our model is shown to better capture changes in VTH/VDD, which are important since VDD and VTH will be key parameters for optimizing device performances for target applications (low power or high performance) in sub-45nm technologies.

Gate-induced-drain-leakage (GIDL) current in 45 nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2 V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping levels. In contrast to the classical GIDL current generated in the gate-to-drain overlap region, the observed GIDL current is generated by the tunneling of electrons through the reverse-biased channel-to-drain p-n junction. A band-to-band tunneling model is used to fit the measured GIDL currents under different channel-doping levels and bias conditions. Good agreement is obtained between the modeled results and experimental data.

Time-based measurements are commonly used for lifetime characterization of semiconductors. We have developed the theory; verified by experiment, of frequency-based lifetime characterization as an alternative to time-based measurements for MOS devices biased in inversion, One consideration during lifetime/diffusion length measurements, is whether the near-surface space-charge region or the bulk or quasineutral region is characterized. To characterize the near-surface space-charge region of the three, one usually makes room temperature pulsed MOS capacitor or diode leakage current measurements, We show that room-temperature, frequency-domain capacitance, conductance, or resistance measurements characterize the quasineutral bulk, not the space-charge region, in contrast to room-temperature pulsed MOS-C or diode leakage curl ent measurements which characterize the space charge region.