The adoption of 5G mmWave is upon us, with major cell phone companies having introduced phones with mmWave capabilities and major US cellphone providers building their infrastructure out. Parts manufactured using Globalfoundries 45RFSOI technology have made significant traction in the infrastructure space. A good part of the success of this technology is based on the excellent high frequency performance of the thin oxide device, the high resistivity substrate and the high voltage support enabled by the use of stacking in SOI technologies. In this paper we introduce a new transistor developed to improve the output power of mmWave power amplifiers (PA). It demonstrates ∼ 1.2X increase in maximum voltage, reduced linear mode resistance and ∼20% increases in fMAX to >400 GHz

5G NR mmWave band PA applications use the high PAPR modulation which requires very low EVM along with a reliable operation at high peak power levels. This work shows the exceptional HCI reliability, linearity and efficiency that 45RFSOI technology offers for mmWave PAs. In particular, the design uses novel PAFET transistor which offers 22% higher voltage handling capability compared to the RVT (Regular Vt) transistor thereby enabling a reliable 10 year lifetime at higher Pout. A differential 2-stack single stage PA design is presented that demonstrates best in class Psat=18.8 dBm with 48% peak PAE, while showing less than 0.1 dB degradation during a 4:1 VSWR stress.

This paper reports the performance of multiple V-band on-chip antennas implemented in Globalfoundries 45nm CMOS SOI process with high-resistivity substrate option. Dipole, slot and loop antennas are implemented as proof-of-concept designs. The antenna samples are flip-chip packaged on a PCB for testing. After de-embedding the loss from the feeding/matching network, the measured boresight antenna gains of the dipole, slot and loop are 3.9dBi, 3.8dBi and 3.7dBi, respectively, matching well with the 3D EM simulations. The measured radiation efficiencies are greater than 79% for all the three cases. Compared to other on-chip/on-package mm-Wave antennas, the demonstrated antennas are fully integrated in CMOS SOI process and do not require any post-processing, substrate-thinning/etching, lossy chip-to-package interconnections, or silicon lenses. It is demonstrated that the high-resistivity substrate option in Globalfoundries 45nm CMOS SOI technology is an effective solution to support high-efficiency and high-performance mm-Wave on-chip antennas, which paves the way for highly integrated mm-Wave transceiver systems including 5G phased arrays and massive MIMO systems.

In this paper, we discuss a DC-20GHz single-pole double-throw (SPDT) transmit/receive switch (T/R switch) design in 45nm SOI process. This circuit is dedicated to fully integrated CMOS RF front end modules for X/Ku band satellite communication applications. The switch exhibits a measured insertion loss of 0.59dB, return loss of 23dB, and isolation of 17dB at 14GHz. The input 1dB compression point is 31.5dBm, and one-tone IIP3 is 63.8dBm. This state of the art performance is comparable or even better than existing commercial GaAs SPDT in this frequency range. The core area is only 90um × 100um, which is very helpful for low cost large element phase array designs.

The total-dose radiation tolerance of 32-nm nFETs is investigated. nFETs built in 32-nm RF-CMOS-on-SOI technology with high-k dielectrics show increased off-state leakage current and electron trapping in the gate oxide. The impact of CMOS-on-SOI technology scaling (from 65-nm to 32-nm) on the total-dose radiation tolerance and hot-carrier reliability (HCR) is investigated through both experiments and supporting TCAD simulations. The 32-nm nFETs exhibit less total-dose degradation compared to 45-nm nFETs. However, the hot-carrier degradation increases as the technology scales. An interplay of electric-field in the gate oxide and impact ionization in the channel region is responsible for the observed differences in the degradation mechanisms for the three technologies.

This paper uses charge deposition by two-photon absorption to present the first investigation of the physical mechanisms underlying the single event transient (SET) response of cascode structures in a 45-nm RF-CMOS/SOI technology, provides the first experimental comparison of SET between 45-nm and 32-nm RF-CMOS/SOI devices, and presents implications for circuit design in both technologies. This work leverages a number of different device types and is supported by calibrated TCAD simulations.

We report the radio frequency (RF) stress reliability response of 45-nm SOI RF nMOSFETs. The dependence of gate oxide degradation and off-state leakage (due to RF stress) on the contact spacing of the Source/Drain (S/D) terminals and the gate finger-to-gate finger spacing is investigated. The RF device performance trade-offs vs. RF stress reliability that result are investigated. Devices with "tight" S/D contact spacing have improved RF performance but worse RF reliability than devices with "loose" S/D contact spacing. Devices with "loose" gate-finger to gate-finger spacing have better RF performance and also better RF reliability. The net result of this investigation is that fundamental tradeoffs between RF performance and reliability exist at these advanced scaling nodes.

The hot carrier and ionizing radiation responses of 45-nm SOI RF nMOSFETs are investigated. Devices with “tight” source/drain (S/D) contact spacing have improved RF performance but degraded hot carrier reliability and radiation tolerance. Devices with “loose” gate finger-to-gate finger spacing have improved RF performance and also improved hot carrier and radiation tolerance. The effects of finger width on the hot carrier stress and ionizing radiation degradation of strained silicon-on-insulator RF MOSFETs are also investigated. Enhanced degradation is observed for devices with wide finger widths and is attributed to the greater channel-region mechanical stress induced impact ionization. This result is contrary to the previous studies which showed that narrow channel width devices should exhibit greater damage. Taken together, these results have serious consequences for RF circuits that require large widths for sufficient RF gain. Finally, devices with symmetric halo doping are observed to exhibit greater total-dose degradation than devices with asymmetric halo doping.

The effects of 63 MeV proton irradiation on 65 nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO 2 ). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. High-frequency measurements show that the input and output matching conditions are not affected, up to a cumulative dose of 4.1 Mrad. The implications of proton irradiation on device design constraints, particularly device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that multi-finger CMOS devices with higher finger width are better-suited for the development of total-dose radiation tolerant analog and RF circuits without additional radiation hardening.

Lateral asymmetric channel doping is applied to 45-nm technology NFET devices. The measured effective drain-current enhancement over coprocessed symmetric control devices is 10%. Analysis reveals that the dominant physical mechanism, which accounts for two-third of the total enhanced drain current, is an 8% increase in the source-side injection velocity. The remaining one-third is attributed to the decreased drain-induced barrier lowering. This paper concludes with an analysis of the switching characteristics of CMOS inverters composed of an asymmetric NFET and a companion symmetric PFET and shows a 5% improvement in the delay. The improvement is explained in terms of the increased velocity and 30% reduction in drain junction capacitance.

The mechanism for ionizing radiation damage in multi-finger SOI CMOS devices is presented for the first time. We analyzed the effects of shallow-trench isolation on ionizing radiation response of 65 nm Silicon-On-Insulator (SOI) CMOS technology. The radiation response of the CMOS devices was investigated using 63 MeV protons and 10 keV X-rays. The implications of proton irradiation and X-ray irradiation on the dc and RF performance of these devices are presented. The cut-off frequency is degraded due to post-irradiation degradation of device transconductance. Even though there is charge-accumulation in the buried-oxide, there is minimal impact on the front-gate characteristics of the partially-depleted SOI devices in this 65 nm CMOS technology. The implications of parasitic conduction along the STI on device design constraints, particularly for varying device width and number of gate fingers, are discussed in the context of high performance RF CMOS technology. These results suggest that body-contacting schemes which eliminate sidewalls (e.g., H-body, T-body) will provide the necessary total-dose radiation tolerance for multi-finger analog and RF devices, without additional hardening techniques.

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (IPEAK) is a key parameter. Ieff is commonly defined as the average between IH and IL, where IH=Ids(Vgs=VDD, Vds=0.5VDD) and IL = Ids(Vgs=0.5VDD, Vds=VDD). In the past, this Ieff definition has been accurate in modeling the inverter delay. However, we find that as devices are scaled further into the nanoscale regime, the maximum transient current can deviate severely from IH, in which case, another metric should be used. The deviation of IPEAK from IH is found to increase as delay decreases or as device overdrive voltage increases. We define Ieff = (IPEAK+IM+IL)/ 3, where IM = Ids(Vgs=0.75VDD, Vds=0.75VDD). We evaluate our model against others by comparing the analytical and HSPICE extracted Ieff ratios across devices of varying threshold voltages, VTH. Our model is shown to better capture changes in VTH/VDD, which are important since VDD and VTH will be key parameters for optimizing device performances for target applications (low power or high performance) in sub-45nm technologies.