This paper presents a fast-prototyping framework for readout circuits designed for a neuromorphic compute-in-memory (CIM) macro utilizing ferroelectric field-effect transistor (FeFET). This framework significantly reduces the development time of CIM macro, particularly in device modeling and layout generation. To achieve this, the framework unifies two software tools: (1) measurement-driven device model generator (MDDMG) and (2) an automated readout circuit layout generator. First, the proposed MDDMG automatically produces a SPECTRE model netlist of the FeFET device from measured I-V data. This model netlist enables schematic simulation of a CIM macro that consists of an FeFET array and analog interface circuits, performing multiply-accumulate (MAC) operation. Second, the automated layout generator produces a DRC/LVS-clean layout of the analog readout circuits, greatly reducing layout development time. To demonstrate the framework, a case study was performed on a 3×8 FeFET based binary CIM array. For this array, the MDDMG generated a model netlist in 22.63 seconds, and the layout generator produced the layout of the readout circuit in approximately 3.7 minutes, substantially reducing the design time and cost associated with developing neuromorphic CIM macros. Furthermore, to verify the layout generator, a test chip was fabricated in 28-nm CMOS technology. Measurement results demonstrate that the auto-generated layout of the readout circuit (transimpedance amplifier and 6-bit successive approximation register analog-to-digital converter) achieved a peak SNDR of 31.35 dB at 100 KS/s, validating the practical use of the proposed framework.

Ferroelectric hafnium-oxide (HfO _2 ) films have revitalized interest in brain-inspired hardware because of their high scalability, compatibility with complementary metal-oxide-semiconductor (CMOS) processes, and suitability for three-dimensional (3D) architectures. This review first analyses the origin, deposition routes, and performance of hafnia-based devices, including ferroelectric field-effect transistor, ferroelectric tunnelling junction and ferroelectric capacitor. As artificial intelligence (AI) continues to advance, the demand for higher memory density becomes increasingly critical. This review presents hafnia-based devices and arrays in both planar and 3D architectures. In 3D structures, the review discusses the principal integration constraints—back-end-of-line (BEOL)-compatible crystallization, conformal atomic layer deposition (ALD) with controlled phase and defects in high-aspect-ratio features, and cross-layer stress together with layer-to-layer variability/disturbance,which collectively determine stackable scalability and influence energy efficiency and training stability, thereby pointing toward compact, energy-efficient, and scalable 3D neuromorphic hardware based on hafnia ferroelectrics.

Three-dimensional (3D) NAND flash memory achieves high density through the vertical stacking of memory cells. However, increasing the number of stacked layers induces significant residual stress, which adversely impacts both structural integrity and electrical characteristics of 3D NAND devices. Thus, effective analysis and management of residual stress in 3D NAND are required. This study employs a Sentaurus technology computer-aided design (TCAD) simulation to examine the effect of residual stress on the reliability of charge-trap 3D NAND. The results show that increasing the compressive stress in the charge-trap nitride (CTN) layer improves data retention through band-edge modulation. To utilize these effects, we propose the insertion of a stress engineering layer (SEL) between the poly-Si channel and surrounding oxide filler. The SEL increases the compressive stress within the CTN layer. Thus, the retention degradation can be reduced. The proposed SEL technique demonstrates the potential to improve the reliability of 3D NAND flash memory by modulating residual stress.

This study investigates the role of positively charged oxygen vacancies in the central region of ferroelectric capacitors and their impact on fatigue. It has been found that, during fatigue, positively charged oxygen vacancies accumulate in the central region, leading to significant degradation in device performance. The application of a high-voltage recovery pulse effectively reverses the charge state of these vacancies from positive to neutral and redistributes them uniformly across the device, restoring its performance. This recovery process is analogous to the ’wake-up’ state of the device, demonstrating its potential to restore electrical performance. The results of this study emphasize the importance of controlling the charge state and distribution of oxygen vacancies in the central region to enhance the durability and functionality of ferroelectric devices. This work provides a pathway for the broader and more effective application of ferroelectric materials in advanced semiconductor devices.

This paper presents interface circuits for 3D FeNAND based compute-in-memory (CIM) arrays, supporting both high-voltage memory operations and low-voltage CMOS logic compatibility. High voltage driver with coarse/fine control ensures wide and fine voltage range control. The source line driver is designed to handle ultra-low current (100pA-100nA) and interface with CMOS circuits safely. All interface blocks were implemented in a 180nm BCD process and validated through measurement and post-layout simulation.

Metal-halide perovskites are emerging as promising semiconductors for next-generation (opto)electronics. Due to their excellent optoelectronic and physical properties, as well as their processing capabilities, the past decades have seen significant progress and success in various device applications, such as solar cells, photodetectors, light-emitting diodes, and transistors. Despite their performance now rivaling or surpassing that of silicon counterparts, halide-perovskite semiconductors still face challenges for commercialization, particularly in terms of toxicity, stability, reliability, reproducibility, and lifetime. In this Roadmap, we present comprehensive discussions and perspectives from leading experts in the perovskite research community, covering various perovskite (opto)electronics, fundamental material properties and fabrication methods, photophysical characterizations, computing science, device physics, and the current challenges in each field. We hope this article provides a valuable resource for researchers and fosters the development of halide perovskites from basic to applied science.

Ferroelectric capacitive memory (FeCAP) holds enormous potential for low-power, high-density in-memory computing. While hafnia-based FeCAPs have attracted attention for their silicon compatibility, they suffer from limited performance, such as a narrow memory window and relatively high switching fields. In this work, an FeCAP device is developed on the basis of a single-crystalline barium titanate (BTO) membrane, a perovskite oxide thin film that can be epitaxially lifted off and transferred onto a silicon platform. By engineering the device structure and epitaxy process, polarization asymmetry is introduced in capacitance-voltage characteristics. The resulting BTO-based FeCAP exhibits superior memory behavior, including a wide memory window of 308 picofarads and a low switching field of 0.005 megavolts per centimeter, outperforming conventional hafnia-based FeCAPs. Furthermore, these properties are preserved after active layer transfer onto a silicon platform. This approach provides a viable pathway for high-quality BTO to integrate into industry-compatible processes and to drive progress in future logic/memory applications.

The ultimate scaling limit in ferroelectric switching has been attracting broad attention in the fields of materials science and nanoelectronics. Despite immense efforts to scale down ferroelectric features, however, only few materials have been shown to exhibit ferroelectricity at the unit-cell level. Here we report a controllable unit-cell-scale domain in brownmillerite oxides consisting of alternating octahedral/tetrahedral layers. By combining atomic-scale imaging and in situ transmission electron microscopy, we directly probed sub-unit-cell-segmented ferroelectricity and investigated their switching characteristics. First-principles calculations confirm that the phonon modes related to oxygen octahedra are decoupled from those of the oxygen tetrahedra in brownmillerite oxides, and such localized oxygen tetrahedral phonons stabilize the sub-unit-cell-segmented ferroelectric domain. The unit-cell-wide ferroelectricity observed in our study could provide opportunities to design high-density memory devices using phonon decoupling.

The threshold-switching behaviors of the synapses lead to energy-efficient operation in the neural computing system. Here, we demonstrated the threshold-switching memory devices by inserting the ZnO layer into the ionic synaptic devices. The EMIm(AlCl3)Cl is utilized as the electrolyte because its conductance can be tuned by the charge states of the Al-based ions. The redox reactions of the Al ions in the electrolyte can lead to the analog resistive switching characteristics, such as excitatory postsynaptic current, paired-pulse facilitation, potentiation, and depression. By inserting the ZnO layer into the EMIm(AlCl3)-based ionic synaptic devices, the threshold switching behaviors are demonstrated. Using the resistivity difference between ZnO and EMIm(AlCl3)Cl, the analog resistive switching behaviors are tunned as the threshold-switching behaviors. The threshold-switching behaviors are achieved by applying the spike stimuli to the device. Demonstration of the threshold-switching behaviors of the ionic synaptic devices has a possibility to achieve high energy-efficiency for the ion-based artificial synapses.

Ferroelectric transistors based on hafnia-based ferroelectrics exhibit tremendous potential as next-generation memories owing to their high-speed operation and low power consumption. Nevertheless, these transistors face limitations in terms of memory window, which directly affects their ability to support multilevel characteristics in memory devices. Furthermore, the absence of an efficient operational technique capable of achieving multilevel characteristics has hindered their development. To address these challenges, we present a gate stack engineering method and an efficient operational approach for ferroelectric transistors to achieve 16-level data per cell operation. By using the suggested engineering method, we demonstrate the attainment of a substantial memory window of 10 V without increasing the device area. Additionally, we propose a displacement current control method, facilitating one-shot programming to the desired state. Remarkably, we suggest the compatibility of these proposed methods with three-dimensional (3D) structures. This study underscores the potential of ferroelectric transistors for next-generation 3D memory applications.

Ferroelectric materials boast a remarkable ability to maintain polarization states independently of external electric fields. This unique trait makes them ideal candidates for manipulating polarization through applied electric fields, effectively influencing the domains within these materials. By modulating polarization states, we gain precise control over channel conductance, rendering ferroelectric materials highly suitable for integration as gate dielectric layers in transistors. The incorporation of ferroelectric layers into transistors enables the regulation of channel conductance, empowering precise control over a device's electrical properties. Consequently, this enhances their effectiveness as memory elements. This innovative approach not only drives the development of high-density memory devices but also bestows ferroelectric transistors with analog memory characteristics. This quality significantly broadens their potential applications, particularly in neuromorphic devices striving to emulate the complexities of biological neural networks. In summary, ferroelectric transistors represent a promising frontier in memory technology, offering not only high-density memory solutions but also the potential to revolutionize the field of neuromorphic computing. This presentation explores these compelling prospects, detailing strategies to fully exploit the capabilities of ferroelectric materials in memory and computational applications.

In this study, we explore how the strategic positioning of conductive yarns influences the performance of plated knit strain sensors fabricated using commercial knitting machines with both conductive and non-conductive yarns. Our study reveals that sensors with conductive yarns located at the rear, referred to as ‘purl plated sensors’, exhibit superior performance in comparison to those with conductive yarns at the front, or ‘knit plated sensors’. Specifically, purl plated sensors demonstrate a higher sensitivity, evidenced by a gauge factor ranging from 3 to 18, and a minimized strain delay, indicated by a 1% strain in their electromechanical response. To elucidate the mechanisms behind these observations, we developed an equivalent circuit model. This model examines the role of contact resistance within varying yarn configurations on the sensors’ sensitivity, highlighting the critical influence of contact resistance in conductive yarns subjected to wale-wise stretching on sensor responsiveness. Furthermore, our findings illustrate that the purl plated sensors benefit from the vertical movement of non-conductive yarns, which promotes enhanced contact between adjacent conductive yarns, thereby improving both the stability and sensitivity of the sensors. The practicality of these sensors is confirmed through bending cycle tests with an in situ monitoring system, showcasing the purl plated sensors’ exceptional reproducibility, with a standard deviation of 0.015 across 1000 cycles, and their superior sensitivity, making them ideal for wearable devices designed for real-time joint movement monitoring. This research highlights the critical importance of conductive yarn placement in sensor efficacy, providing valuable guidance for crafting advanced textile-based strain sensors.

Hafnia-based ferroelectrics have gained much attention because they can be used in highly scaled, advanced complementary metal-oxide semiconductor (CMOS) memory devices. However, thermal stability should be considered when integrating hafnia-based ferroelectric transistors in advanced CMOS devices, as they can be exposed to high-temperature processes. This work proposed that doping of Al in hafnia-based ferroelectric material can lead to high thermal stability. A ferroelectric capacitor based on Al-doped hafnia, which can be used for one-transistor-one-capacitor applications, exhibits stable operation even after annealing at 900 °C. Moreover, it demonstrates that the ferroelectric transistors based on Al-doped hafnia for one-transistor applications, such as ferroelectric NAND, retain their memory states for 10 years at 100 °C. This study presents a practical method to achieve thermally stable ferroelectric memories capable of enduring high-temperature processes and operation conditions.

Ferroelectric transistors based on hafnia-based ferroelectrics have emerged as promising candidates for next-generation memory devices. Additionally, hafnia-based ferroelectric transistors are suggested for three-dimensional (3D) memory devices, such as 3D ferroelectric NAND. This paper investigates the utilization of poly-Si as a gate material for hafnia-based ferroelectric transistors in 3D NAND structures. Conventional gate materials, such as TiN or W, are usually deposited in 3D NAND structures by using the gate-last process, which requires an additional gate replacement process. We demonstrate that poly-Si can be used as a gate material for hafnia-based ferroelectric transistors. We show that the 3D ferroelectric NAND based on the poly-Si gate can be fabricated by a simpler gate-first process without requiring a gate replacement process. Our findings underscore the potential of poly-Si as a gate material for ferroelectric transistors and 3D ferroelectric NAND.

Hafnia-based ferroelectric thin-film transistors (FeTFTs) hold promise for next-generation memory applications like three-dimensional (3D) NAND flash memory, owing to their low power and high-speed operation. However, the utilization of polycrystalline Si (poly-Si) channels imposes limitations on the on-current of the device due to its low mobility. Consequently, alternative channel materials and diverse device engineering methods are being explored. In this study, we fabricated a FeTFT utilizing a poly-Si channel with aligned grains, achieved through the crystal-filtered (CF) metal-induced lateral crystallization method. The CF poly-Si channel exhibited an increase in on-current compared to conventional poly-Si channels. Additionally, the FeTFT employing CF poly-Si demonstrated a memory window of 3.2 V and a switching speed of 50 ns. This study represents a significant advancement in the field of FeTFTs and holds potential for application in next-generation electronic devices, particularly in 3D NAND flash memory, display, and neuromorphic device applications.

We introduce a novel method for fabricating perovskite solar modules using selective spin-coating on various Au/ITO patterned substrates. These patterns were engineered for two purposes: (1) to enhance selectivity of monolayers primarily self-assembling on the Au electrode, and (2) to enable seamless interconnection between cells through direct contact of the top electrode and the hydrophobic Au connection electrode. Utilizing SAMs-treated Au/ITO, we achieved sequential selective deposition of the electron transport layer (ETL) and the perovskite layer on the hydrophilic amino-terminated ITO, while the hole transport layer (HTL) was deposited on the hydrophobic CH3-terminated Au connection electrodes. Importantly, our approach had a negligible impact on the series resistance of the solar cells, as evidenced by the measured specific contact resistivity of the multilayers. A significant outcome was the production of a six-cell series-connected solar module with a notable average PCE of 8.32%, providing a viable alternative to the conventional laser scribing technique.

Ferroelectric transistors are considered promising for next-generation 3D NAND technology due to their lower power consumption and faster operation compared to conventional charge-trap flash memories. However, ensuring their suitability for such applications requires a thorough investigation of array-scale reliability. This study specifically examines the suitability of hafnia-based ferroelectric transistors for advanced 3D NAND applications, with a specific focus on establishing a disturb-free voltage scheme to ensure the reliability of ferroelectric transistors within the array. Our key finding highlights the crucial role of optimal pass voltage in achieving disturb-free operation in both 2D and 3D ferroelectric NAND arrays. Additionally, the study indicates that read disturb remains negligible when an appropriate read voltage is applied. These insights provide a practical strategy for achieving reliable operation in 2D and 3D ferroelectric NAND, highlighting the potential of hafnia-based ferroelectric materials to meet the evolving requirements of high-density and reliable NAND flash memory applications.

The solution-processed and conductive MoO3–PEDOT:PSS (Mo–PPSS) composite layer in a MoO3/Au/MoO3–PEDOT:PSS (MoAu/Mo–PPSS) multilayer electrode in ITO-free organic solar cells (OSCs) was optimized in terms of electrical conductivity, interfacial contact quality, work function, and process wettability of the conductive composite thin film. The surface composition of the PEDOT:PSS film onto different electrodes was observed by using X-Ray Photoelectron Spectroscopy. The PEDOT:PSS-MoO3 composite protects the dissolution of individual MoO3 with PEDOT:PSS, which was confirmed by Auger Electron Spectroscopy. The UV-Visible spectroscopy showed that the photoactive layer of P3HT:PCBM absorbs in the wavelength range of 300–650 nm with the maximum absorption at 515 nm (2.40 eV). The device performance of 3.97% based on an MoAu/Mo–PPSS conductive composite electrode exhibited comparable enhancement and only 6% enhancement compared to an ITO-based electrode (3.91%). The enhancement of device efficiency was mainly due to relatively higher conductivity, a low work function of the conductive metal oxide-metal-metal oxide/polymer composite, and an enhancement of interfacial contact quality between the hole transport layer (HTL) and the mixed organic polymeric photoactive layer. These results indicate that the solution-processable Mo–PPSS conductive composite layer of the MoO3/Au multilayer electrode can replace the ITO-based electrode in the bulk of heterojunction organic photovoltaics (OPVs).

Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because ${n}$ -type oxide semiconductors cannot provide sufficient hole carriers to realize ferroelectric polarization switching. To solve this issue, a novel design strategy is proposed to achieve increased polarization switching while maintaining the stability of oxide semiconductor-based ferroelectric thin-film transistors (FeTFTs). By inserting an additional ${p}$ -type CuOx layer between the ${n}$ -type oxide semiconductor InZnOx and ferroelectric HfZrOx, increased polarization switching is achieved owing to the high electron and hole densities in the InZnOx and CuOx layers, respectively. Thus, a memory window of 4 V is achieved, which cannot be obtained using a single oxide-semiconductor channel. We also demonstrate that the proposed method is viable for three-dimensional ferroelectric NAND (3D FeNAND) devices. In 3D FeNAND, replacing the dielectric filler with ${p}$ -type CuOx maximizes polarization switching and enlarges the memory window. The results demonstrate a novel structure and fabrication method for high-performance FeTFTs for advanced 3D non-volatile memory applications.

Liquid-based devices have emerged as bioinspired neuromorphic applications owing to their high ion-diffusion coefficients, diverse structures, and controllable ion-exchange reactions. By engineering and modifying liquid materials, multifunctional liquid-based computing devices have been developed for next-generation memory and neuromorphic devices. The unique properties of liquids make them feasible for memory functions and various synaptic applications, such as emulating synaptic plasticity, homeostasis, and action potentials. Utilizing liquids in computing devices provides a promising and versatile platform for high-performance memory devices and enables the emulation of bioinspired computing functions. In this Spotlight, we highlight recent advances in liquid-based memory devices and focus on synaptic applications. We then discuss possible array structures and scaling-down technologies for liquid-based devices. Finally, the challenges and future prospects of liquid-based devices are discussed.