UUltrathin p-type capping layers were introduced to modulate the back-channel surface of IGZO thin-film transistors (TFTs). Among Te, NiOx, and SnOx capping layers, the Te-capped IGZO TFT exhibits the best balanced performance, with a subthreshold swing (SS) of 67.1 mV/dec, a field-effect mobility (μFE) of 25.6 cm2/V·s, an on/off current (Ion/Ioff) ratio of 1.06×109, and a threshold voltage (VTH) of −0.035 V. Compared with the control device, Te capping reduces SS by 63%, enhances μFE by 43%, and shifts VTH positively by 0.945 V. The Ion/Ioff ratio also increases by 49.3 times. The 2-nm Te layer therefore enables simultaneous improvement in switching steepness, carrier transport, and VTH control through back-channel modulation.
In this work, we successfully fabricated p-channel optimized metallic source/drain Schottky barrier fully depleted silicon-on-insulator (O-MSD SB FDSOI) MOSFETs that perform comparably to or better than conventional raised source/drain (RSD) devices. Process optimization focused on hole Schottky barrier height (SBH) modulation in NiSi/n-Si Schottky junction diodes (SJDs) through silicide-induced dopant segregation (SIDS) and silicide-as-diffusion-source-induced dopant segregation (SADS). Dopant segregation (DS) forms a locally heavily doped "P+" region at the silicide/Si interface, thereby modulating the barrier profile to suppress off-state leakage and enhance on-state tunneling. In addition, we modified the SADS process to develop M-SADS and applied it to fabricate p-channel O-MSD SB MOSFETs, which exhibit effective gate-induced drain leakage (GIDL) suppression and achieve an on/off current (Ion/Ioff) ratio of 5.7×10⁸. These results demonstrate a process-level optimization for the studied FDSOI platform and indicate the potential for high-performance and low-power applications.
Oxide semiconductor FeFETs (OS-FeFETs) suffer from inefficient erase operation due to limited positive-charge supply from the OS channel. Here, a length-scaling polarization extraction (LSPE) method is proposed to separate switchable-polarization contributions from the floating-body MFIS region and MFISM gate-to-source/drain (S/D) overlap regions. Devices annealed before channel deposition show an unstable memory window (MW) and suppressed PMFIS, indicating inefficient polarization reversal in the OS-channel-coupled region. Crystallization annealing after channel deposition enhances both components and stabilizes the MW. O 1s XPS results show an increased oxygen-vacancy-related component, suggesting enhanced donor-state-assisted positive-charge supply. These findings provide a viable pathway to improve erase efficiency and MW stability in OS-FeFETs for nonvolatile memory applications.
Enhancement-mode (E-mode) β-Ga2O3 transistors are highly desired for kV-class power switching, but their realization remains challenging due to the lack of effective p-type doping. Fin- and trench-gate structures have been employed to achieve the E-mode operation, but they suffer gate-corner electric-field (E-field) crowding and thereby reliability concerns. Here we propose the deployment of the current aperture vertical electron transistor (CAVET) architecture to shield the trench-gate from high E-field. The fabricated trench-gate CAVET achieves a threshold voltage of 2.1 V, a small transfer hysteresis of 50 mV, a specific on-resistance of 13.4 mΩ·cm2, and a breakdown voltage of 1140 V. Its stability is investigated under high-bias drain stress, presenting small parametric shifts after 600 V stress for 1000 s. When elevating the stress bias to 1000 V, the device presents no gate failure, validating the effective E-field shielding. Notably, such high-bias stability tests have not been previously reported for Ga2O3 vertical transistors. Therefore, this work demonstrates a promising architecture for normally-off, kV-class β-Ga2O3 power transistors with high-voltage drain-stress stability.
The large-scale integration of solid-state quantum computing systems is limited by the available cooling power at deep-cryogenic temperatures, imposing stringent requirements on the switching efficiency of control electronics. Bulk-Si CMOS remains a leading candidate for scalable cryo-CMOS platforms; however, the saturation of the subthreshold swing (SS) at deep-cryogenic temperatures restricts circuit performance. This behavior is primarily attributed to band-tail states arising from interfacial disorder and potential fluctuations. In this letter, we experimentally demonstrate atomic-scale interface engineering using a tailored high-pH fluoride treatment to form an atomically smooth Si/SiO2/HfO2 interface, thereby mitigating the associated band-tail states. The resulting bulk-Si NMOSFETs achieve a SS of 8.9 mV/dec at 4.2 K, together with a 27% reduction in characteristic tail energy and a 20% improvement in peak field-effect mobility. These results demonstrate the importance of atomic-scale interface engineering for mitigating band-tail states and improving the switching efficiency of bulk-Si/high-κ cryo-CMOS devices.
Bio-inspired visual systems, owing to their event-driven operation, rapid response, and low-power processing capabilities, have emerged as promising candidates for next-generation efficient visual processing architectures. However, existing bio-inspired visual systems frequently employ rate coding, which necessitates a large number of spikes, thereby leading to high energy consumption and latency. This work demonstrates a compact single-spiking visual neuron and system based on a VO2 memristor. With a feedback-controlled leaky integrate-and-fire circuit, the neuron emits only one spike under each input stimulus. By further introducing an optical sensor into the input path, illuminance can be directly encoded into spike timing. In simulations, the resulting single-spike visual system achieves 92.88% accuracy on the Modified National Institute of Standards and Technology (MNIST) classification task, while reducing the average energy consumption and average decision time by 12.2× and 2.96×, respectively, compared with rate coding. These results indicate that the proposed neuron and system provide a new route toward efficient neuromorphic visual systems.
To mitigate the electric field crowding at the Schottky contact edge that limits the breakdown performance of β-Ga2O3 vertical Schottky barrier diodes (SBDs), a thermally reflowed photoresist-based beveled field plate (BFP) structure is proposed. The naturally formed small-angle profile after reflow is directly used as the FP dielectric, eliminating additional deposition and etching process. Experimental results demonstrate that the thermally cured photoresist exhibits a stable relative dielectric constant of ~3.5 and significantly improves the insulating and high-temperature characteristics. With the FP structure, the extracted Schottky barrier height exceeds 1.29 eV, and the breakdown voltage (BV) is significantly improved from 785 V to 2225 V, yielding a power figure of merit (PFOM) of 1.123 GW/cm2. TCAD simulations further elucidate the impact of field plate thickness, length, and bevel angle on electric field redistribution, confirming that the small-angle geometry effectively suppresses peak electric field at the device edge. The proposed strategy provides a low-cost and process-simplified solution for high-performance β-Ga2O3 power devices.
We implement experimentally a relativistic Ka-band gyrotron with maximum output power level of about 1.7 MW. Based on 3D PIC simulations, we show that the increase in pitch factor of the electron beam leads to a transition from stationary to multi-frequency operation regimes due to simultaneous excitation of neighboring axial modes. In experiments, we register radiation with a frequency-comb-like spectrum comprising 7 spectral components. The distance between the spectral lines is about 225 MHz with central frequency of about 28.2 GHz and the mean radiation power is about 100 kW.
This work introduces the concept of metatransistors, which decouples the DC and RF access resistances of a transistor to enable efficient sub-THz power amplification. The device integrates patterned Schottky contacts, coupled to the 2DEG through an ultra-thin insulating barrier, forming a metal-insulator-2DEG metastructure. This structure supports slow waves that confine the RF current injection near the gate as the frequency increases, reducing the RF access resistance (Racc,RF) while leaving the DC access resistance (Racc,DC) — and thus the bias current — unaffected. Increasing the number of fingers further enhances this confinement through their collective interaction, compensating the gate-resistance penalty of periphery scaling. Fabricated metatransistors exhibited up to 50×-smaller Racc,RF than Racc,DC and an ultra-low RF contact resistance of 0.02 Ω·mm, remaining flat above 150 GHz, and achieved fMAX of 285 GHz while dissipating 51% less DC current than the reference HEMT at the same bias voltages. Load-pull measurements at 160 GHz yielded a peak output power of 0.95 W/mm and a peak PAE of 15.1% — a 68% improvement over the reference HEMT. These results establish metatransistors as a promising route toward ultra-low RF contact resistance and efficient mmWave/sub-THz power amplification.
The coupling effects of out-of-plane (OOP) and in-plane (IP) polarization in two-dimensional α-In₂Se₃ based ferroelectric semiconductor-field effect transistor (FeS-FET) are revealed based on TCAD simulation. It is found that single-directional OOP or IP polarization cannot effectively modulate the device state. In contrast, the coupled OOP and IP polarizations significantly regulate the electric field and carrier distribution within FeS channel, endowing a large memory window and a high on/off ratio, which can be attributed to the synergistic enhancement effect of coupled OOP/IP polarization. These results give new insights into operation mechanism and optimization design of FeS-FET as novel ferroelectric memory.
This paper presents a vertical GaN trench MOSFET featuring Variable Lateral Ion-implanted Guard Rings (VLGR) formed in a partially thinned p-GaN region to engineer the edge electric field distribution. The proposed graded termination effectively mitigates electric field crowding, enabling a breakdown voltage (BV) of 2305 V—an approximately 2.7-fold improvement over the Ref-MOSFET (850 V). The fabricated device exhibits a threshold voltage (VTH) of 4.9 V, a specific on-resistance (Ron, sp) of 7.2 mΩ·cm2, and an on/off current ratio of 107, yielding a Baliga’s figure of merit (BFOM) of 738 MW/cm2. These results demonstrate an effective edge-termination strategy for extending the blocking capability of fully vertical GaN trench MOSFETs and suggest the potential of this structure for high-voltage power electronics applications.
Al0.6Ga0.4N-channel HEMTs with Schottky gates, dual field plates, and SiO2 passivation were fabricated on sapphire substrate. For devices with a gate-to-drain spacing of 5 μm, the average on-resistance was 20.3 Ω.mm (1.67 mΩ.cm2). A peak transconductance of 43 mS/mm and a maximum breakdown voltage of 1020 V were achieved, with low gate leakage current. Pulsed I-V measurements performed at VDS,Q = 40 V with a 100-μs pulse width showed no measurable current collapse. Under hard switching conditions, transient dynamic onresistance (RON,DYN) was then measured after 10-ms off-state stress at 40, 400, and 600 V. The lowest measured RON,DYN increases were 7%, 26%, and 31% after 40-, 400-, and 600-V stress, respectively, within 200 μs after switching. Under 1000-cycles of 400-V off-state stress, the dynamic on-resistance increase reached a maximum of 58% after approximately 450 cycles and then decreased to 52% after 1000 cycles. No permanent degradation in output current or gate leakage current was observed after 1000 stress cycles, indicating the promising high-voltage dynamic robustness of UWBG AlGaN-channel HEMTs for power switching applications.
We report a 4-transistor (4T) Ternary Content Addressable Memory (TCAM) that significantly reduces the physical footprint by employing dual-gate IGZO transistors. High-density TCAMs are essential components for memory augmented neural networks and advanced computing systems; however, the large physical footprint remains a significant limitation in conventional designs. The proposed TCAM unit cell adopts a simplified structure, reducing the transistor count to four, which is substantially lower than previous SRAM-based (16T) and oxide semiconductor-based (6T) counterparts. Moreover, connecting the search line directly to the gate electrode effectively mitigates IR drop, enhancing the design’s suitability for large-scale memory applications. Experimental results validate the proposed design, demonstrating accurate Hamming distance computations (155.9 nA/bit), high endurance (>1010 cycles), and fast operation with 350 ps search latency and 220 ns write time.
On-chip electrochemical devices hold great promise for functional diversification through monolithic integration with semiconductor integrated circuits (ICs). However, their practical implementation is hindered by conventional liquid electrolytes, which are incompatible with standard IC fabrication processes. Although recently developed semi-liquid gel electrolytes enable on-chip deposition, their poor wafer-scale depositability and patternability severely restrict device miniaturization and high-density integration. Herein, we propose a photolithographic patterning method for ionic liquid gel (iongel) electrolytes to achieve high ionic conductivity and scaling capability simultaneously. A complete wafer-level iongel thin-film deposition and dry-etching fabrication workflow is developed. Leveraging the patterned iongel electrolyte, the fabricated on-chip electrochemical micro supercapacitors achieve record-high areal device density of 400 cells/cm² and areal voltage density of 800 V/cm², while retaining a stable areal capacitance density over 1.2 mF/cm² and satisfactory operational reliability.
Thin-film acoustic wave devices have substantially improved performance through bottom substrate-stack engineering, which leaves the vulnerability of interdigital transducers (IDTs) a critical challenge, especially under high-power excitation and top-space perturbations. By introducing cladding multilayers above the IDTs on a piezoelectric thin film, layered acoustic wave (LAW) devices with a symmetric acoustic-reflection structure provide strong vertical energy confinement and environmental isolation for the target modes. This architecture unlocks the top space above the IDTs for flexible functionalization. As a representative demonstration, this work presents a polymer-functionalized LAW prototype, showing that mature packaging pipelines can be simplified when inherently suppressing high-frequency, higher-order bulk wave spurious modes. With dispersion analysis and simulation, the low-acoustic-velocity and high-damping polymer is verified to be an effective medium for guiding and absorbing leaked bulk waves. The fabricated resonators provide dual functionality: spurious suppression and enhancement of the quality factor (Q) without degrading electromechanical coupling of the targeted mode. This work highlights the strong potential of versatile top-space stacking on LAW devices beyond conventional thin-film surface acoustic wave platforms.
We demonstrate an all-phase-change artificial neural network in which phase-change memory (PCM) devices simultaneously realize synaptic plasticity and reconfigurable activation-function artificial neurons. Precise control of the voltage-amplitude step size during the SET and RESET processes enables gradual conductance modulation, thereby realizing synaptic long-term potentiation (LTP) and long-term depression (LTD). More importantly, threshold switching behavior induced by larger pulse widths and larger voltage steps allows the realization of reconfigurable activation functions, including ReLU, sigmoid, and softplus. System-level simulations on the MNIST dataset demonstrate recognition accuracy exceeding 98%, comparable to those achieved using ideal software-defined activation functions, thereby validating the robustness and reliability of the all-PCM neural network. These results highlight the strong potential of PCM devices for highly integrated and multifunctional neuromorphic computing systems.
This study demonstrates high voltage (HV), back-end-of-line (BEOL)-compatible, top-gate In2O3 transistors designed for scalable on-chip power converters in monolithic-3D (M3D) systems. 8-nm-thick In2O3 transistors exhibit current modulation ratio (ION/OFF) > 107, subthreshold swing (SS) ≈ 108 mV/dec, on-resistance (RON) ≈ 0.48 Ω·mm2, and breakdown voltage (VBD) ≈ 414 V. While threshold voltage (VTH) remains stable under positive/negative bias temperature stress (PBTS/NBTS) even at 85 °C, the devices exhibit unconventional on-current ( ION) loss under NBTS and pronounced ION collapse under hot carrier stress. These ION degradations are greatly mitigated by passivating the access-region. This study reveals the dual-edged effect of the access region in HV oxide transistors in enabling high-voltage operation while triggering reliability penalties and establishes passivation as a practical route to mitigate ION degradation.
