As the semiconductor technology matures from research to development and eventually entering manufacturing, there is a consistent focus on reducing defects and yield detractors. This results in engineers utilizing the Failure Mode and Effects Analysis (FMEA) duplicate of integrated circuits. In failure analysis (FA) of integrated circuits, Scanning Capacitance Microscopy (SCM) has been used to identify failure mechanisms, such as regions of incorrect doping and electrical shorts, thereby indicating the appropriate corrective actions required to remedy the device. Because sample preparation and data interpretation are relatively straightforward, FA applications of SCM can be performed with quick turnaround and with few ambiguities that can arise in quantitative applications. In this chapter, we will focus on SCM applications, highlighting work performed at the state-of-the-art chip manufacturing facility of GLOBALFOUNDRIES.

Probing the distribution of charge carriers in semiconductor device structures is of crucial importance to better understand semiconductor fabrication processes and how they affect the incorporation, diffusion and activation of dopants and hence the final device performance. Scanning spreading resistance microscopy (SSRM) has emerged as the most valuable technique for 2D and 3D carrier mapping in semiconductor device structures due to its excellent spatial resolution, sensitivity and ease of quantification. The present chapter first introduces the principles of the technique, thereby discussing the underlying physical mechanisms such as the nanometer-size probe-semiconductor contact. Faced with the stringent requirements imposed by advanced 3D device architectures, novel approaches and concepts such as 3D carrier profiling and fast Fourier transform-SSRM (FFT-SSRM) have been developed in the recent years. These methods aid in extending conventional SSRM toward quantitative carrier profiling in aggressively scaled 3D device structures which is illustrated on the example of selected relevant applications such as FinFETs and nanowire-based transistors.

Inline electrical testing in a semiconductor fabrication line is a very common method to monitor the line performance and to be able to detect any issue for the tested wafers. This helps to detect the problems much earlier. Detecting issues earlier not only stops the affected wafer from processing further, but it would be able to highlight an upstream process issue stopping other incoming wafers. Fundamental issues like high probe contact resistance (CRES) during test affects the measurement data integrity of critical device parameters. This also impacts the learning cycles as well as mean time to detect process / drift issues. Extensive data collection and experiments were able to conclude that the presence of copper oxide is the root cause of high CRES. Adhesion to different constructs explains variations seen in different designs.

As technology scaling continues, the selection of materials for sacrificial hard masks become very critical. Sacrificial hard masks are thin films that are used for patterning or protecting critical underlying films from damage during various processes like etching, deposition or planarization. In this article, we discuss the effect of the sacrificial hard mask material on the erosion in the self-aligned via (SAV) patterning process, selectivity in the etch process, adhesion, defectivity, and metallization.

A method is suggested to prepare lamella for quantitative electron holography by focused ion beam without the need for postprocessing. It relies on thinning of a lamella from the back side of the Si substrate and removal of the protective layers with Ga ions with progressively lower energies down to 2 kV. It is shown that variations of the dopant potential across a one-dimensional p+/n junction in Si, which are derived by electron holography and from the results of secondary ion mass spectrometry, agree to much better values than 50 mV. The effect of the protective layer deposited during TEM sample preparation on the results of electron holography was evaluated. The Si oxide protective layer, which was deposited onto the Si surface, showed a limited charging effect while oxidizing the top of the Si surface. The carbon protective layer showed no surface erosion, yet it has revealed strong charging effects. The deposition process of the protective layer needs to be optimized for a given application in future work.

Nanosecond laser-induced grain growth in Cu interconnects is demonstrated for the first time using 14nm FinFET technology. We achieved a 35% reduction in Cu interconnect resistance, which delivers a 15% improvement in RC and a gain of 2 – 5% in I Dsat . Additionally, reliability was enhanced with an improvement in dielectric VBD and Cu EM performance without impacting the ULK mechanical integrity. Our results demonstrate a path to extending Cu interconnects for performance boost in 14nm FinFETs and beyond.

With each new advanced technology node, minimum feature sizes continue to shrink. As a result, the devices become denser and exposure tool's depth of focus decreases - making lithography one of the most crucial modules in the process flow. Hence, the elimination of hot spots triggered by problematic pattern regions based on optical simulation, by cleaning wafer backside is a critical issue that needs to be addressed to prevent significant yield degradation.

Abstract This paper discusses the Failure Analysis methodology used to characterize 3D bonded wafers during the different stages of optimization of the bonding process. A combination of different state-of-the-art techniques were employed to characterize the 3D patterned and unpatterned bonded wafers. These include Confocal Scanning Acoustic Microscopy (CSAM) to determine the existence of voids, Atomic Force Microscopy (AFM) to determine the roughness of the films on the wafers, and the Double Cantilever Beam Test to determine the interfacial strength. Focused Ion Beam (FIB) was used to determine the alignment offset in the patterns. The interface was characterized by Auger Spectroscopy and the precession electron nanobeam diffraction analysis to understand the Cu grain boundary formation.

With the transition from planar to three-dimensional device architectures such as FinFets, TFETs and nanowires, new metrology approaches are required to characterize the 3D-dopant and carrier distributions precisely, as their positioning relative to gate edges, 3D-distribution, conformality, and absolute concentration determine the device performance in great detail. Concepts like atomprobe tomography with its inherent 3D-resolution are obviously a potential solution although its routine application is still hampered by localization problems, reconstruction artifacts due to inhomogeneous evaporation, sensitivity due to the limited statistics, poor tip yield, etc. Although on the other hand concepts like scanning spreading resistance microscopy are inherently 2D, extensions towards 3D appear possible either by the design of dedicated tests structures or by novel approaches such as mechanical scalping. Ultimately even 1D-methods like secondary ion mass spectrometry can be used to study dopant incorporation in 3D-structures. When assessing their performance as metrology tool for 3D-devices and structures one needs to address not only their ability to achieve 3D-spatial resolution but also the physical property which is probed, i.e. dopants versus carriers, as well as the complexity of the method used. An evaluation in terms of time to data is equally important as the technical capabilities. The application of these methods to 3D-structures and confined volumes, has demonstrated that the changing surface/volume ratios in confined devices versus blanket films lead to phenomena (dopant deactivation, enhanced diffusion,..) which cannot be observed in blanket experiments. Hence more emphasis should be placed on the analysis of device and structures with the relevant dimensions relative to the exploration of blanket experiments. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

This work presents the properties and applications of high vacuum scanning spreading resistance microscopy (HV-SSRM) for two-dimensional carrier profiling. Characteristics of this concept in terms of spatial resolution and dopant gradient resolution as well as in terms of concentration sensitivity and quantification procedures are briefly presented. Insight in process optimization and junction engineering is demonstrated by linking the carrier profiles extracted from HV-SSRM technique with electrical device performance for a laser-only p-MOSFET lot targeting the 32 nm node.

With the continued scaling of CMOS devices down to 32nm node and beyond, device performance is very sensitive to the lateral diffusion mechanisms influencing the effective channel length. Tools are thus, required to measure with sufficient resolution and accuracy the carrier distribution. Scanning spreading resistance microscopy (SSRM) has evolved as a successful carrier-profiling technique with sub-nm resolution, less than 2 nm/decade gradient resolution and high dynamic range 1015 to 1021 cm-3. In this work, we present the approaches (methodology and special test structures) to obtain a 3D-carrier concentration map for FinFET-based devices. We also correlate the results obtained with SSRM for various process conditions and its implications on device performance.

We developed a procedure and software allowing us to predict and understand device performance by incorporating 2D-carrier profiles from high resolution scanning spreading resistance microscopy into a device simulator. We demonstrate the incorporation of the quantified SSRM 2D-profiles into a device simulator using data collected on p-MOSFETs. Based on these profiles the simulator now predicts the electrical characteristics of the device in excellent agreement with the experimental device results, whereas calculations based on (advanced calibration) process simulations showed significant discrepancies. With this approach the difficult and time consuming calibration step of the process simulation can be circumvented and device results can be interpreted directly based on the details of the real 2D-carrier profiles.

With the continuous shrinking of transistors and advent of new transistor architectures to keep in pace with Moore's law and ITRS goals, there is a rising interest in multigate 3D-devices like FinFETs where the channel is surrounded by gates on multiple surfaces. The performance of these devices depends on the dimensions and the spatial distribution of dopants in source/drain regions of the device. As a result there is a need for new metrology approach/technique to characterize quantitatively the dopant distribution in these devices with nanometer precision in 3D. In recent years, atom probe tomography (APT) has shown its ability to analyze semiconductor and thin insulator materials effectively with sub-nm resolution in 3D. In this paper we will discuss the methodology used to study FinFET-based structures using APT. Whereas challenges and solutions for sample preparation linked to the limited fin dimensions already have been reported before, we report here an approach to prepare fin structures for APT, which based on their processing history (trenches filled with Si) are in principle invisible in FIB and SEM. Hence alternative solutions in locating and positioning them on the APT-tip are presented. We also report on the use of the atom probe results on FinFETs to understand the role of different dopant implantation angles (10° and 45°) when attempting conformal doping of FinFETs and provide a quantitative comparison with alternative approaches such as 1D secondary ion mass spectrometry (SIMS) and theoretical model values.

The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.

A solution for conformal n-type finFET extension doping is demonstrated, yielding I ON values of 1.23 mA/μm at I OFF =100 nA/um at 1V. This high device performance results from 40% reduced external resistance, which in term is stemming from 130% increased fin sidewall doping (confirmed by SIMS, SSRM and Atom Probe) relative to ion implant process. In this work we also report lowered gate leakage due to the damage-free extension doping.