As the minimum pitch in interconnects continues to shrink, dielectric breakdown is becoming increasingly more difficult to qualify for each new technology node. Standard voltage-acceleration models provide quick, but general, assessments of the dielectric quality. Instead, a one-dimensional charge transport model has been developed as a tool to investigate the process of the dielectric breakdown and why it occurs. The model couples Poisson's equation with constitutive equations for mobile electrons, trapped electrons, and defects in the dielectric. Bonds in the dielectric matrix are weakened by the electric field, and broken by energetic electrons, creating defects. Failure occurs when a critical defect density is reached, causing trap-to-trap tunneling and an abrupt increase in the current. The model successfully replicates electrical data for leakage current and dielectric failure as a function of voltage, temperature, and thickness. The activation energy for dielectric failure is shown to increase as the electric field decreases, resulting in much higher activation energies at operating conditions compared to testing conditions. The dielectric strength also increases for decreasing thickness based on a previous theory for planar dielectrics, and is shown to cause the failure vs. field slope to increase for thinner dielectrics.

Nanosecond laser-induced grain growth in Cu interconnects is demonstrated for the first time using 14nm FinFET technology. We achieved a 35% reduction in Cu interconnect resistance, which delivers a 15% improvement in RC and a gain of 2 – 5% in I Dsat . Additionally, reliability was enhanced with an improvement in dielectric VBD and Cu EM performance without impacting the ULK mechanical integrity. Our results demonstrate a path to extending Cu interconnects for performance boost in 14nm FinFETs and beyond.

Non-Poisson area scaling behavior has long been observed in BEOL (Back End Of Line) and MOL (Middle Of Line) Time-dependent dielectric breakdown (TDDB) reliability tests due to known variations across the wafer. Three different statistical models have been proposed to accurately account for this non Poisson behavior. In this work, a new methodology for proper area scaling treatment is systematically studied by both experiments and Monte Carlo simulations. A more realistic and robust method is then proposed, for a more accurate reliability projection.

Continued scaling dimensions of interconnects used for Si chip integration reduces the available cross sectional area for conduction. As Cu requires a protective diffusion barrier, TaN and a liner such as Co or Ru is frequently chosen to fulfill the various requirements such as time dependent dielectric breakdown (TDDB). Due to the higher resistivity, scaling the barrier/liner thickness with the line dimension is desirable, but has proven difficult much below 2nm. One aspect here is the limited conformality when using physical vapor deposition (PVD) as the method of choice. Conformal methods such as atomic layer deposition (ALD) have been studied extensively as well for this application. In this paper, we investigate the limits of PVD TaN thickness scaling while maintaining Cu diffusion barrier properties. For this purpose, a planar metal-insulator capacitor has been employed for TDDB testing which was specifically designed to avoid any process related damage to the low-k dielectric. The TaN range examined here was between 0.2 to 3nm, deposited by a PVD process with low input power in order to control deposition accurately below 1nm thickness. It is found that both Co and Ru can add significantly to the TaN barrier integrity. The results further suggest that TaN can be thinned to less than 0.8nm and yet maintain barrier integrity. In particular the combination of TaN and Ru was found to show excellent barrier properties, with TaN as thin as 0.5nm. The impact on line and via resistance between 12 and 24nm wide is being discussed.

Electromigration reliability of BEOL Cu interconnects with various metal line widths and via sizes has been studied. EM lifetime significantly improves from minimum width to three times the minimum width, and then saturates. In addition, the EM lifetime of the wide metal lines was not dependent on via size. The proposed mechanism for EM lifetime improvement is larger grains in wider lines leading to a suppression of grain boundary diffusion. Cu grain size and Cu drift velocity were correlated to the EM lifetime behavior, saturating at the same line width, and kinetic studies found activation energies consistent with grain boundary diffusion.

Recently a BEOL (Back End Of Line) and MOL (Middle Of Line) Time-dependent dielectric breakdown (TDDB) reliability test and fail rate projection methodology based on large data analysis was proposed and studied. However the extraction of one of the key model parameters, the field acceleration factor Y e was ambiguously defined. If no enough caution is taken, a systematically lower γ E will be obtained which leads to a pessimistic projection. In this work, the fundamental differences with two different extraction methods are systematically studied by both experiments and Monte Carlo simulations. A more realistic and robust method is then proposed, for a more accurate reliability projection.

This paper presents the impact of Through Silicon Via (TSV) process on wafer level reliability with respect to front-end of line (FEOL) and back-end of line (BEOL) reliability aspects. A TSV proximity study was performed by placing the TSV at various keep-out zone (KOZ) distances and different orientations of horizontal, vertical, and 45 degrees. FEOL and BEOL test structures were designed using stand-alone devices having TSV at KOZ distance of 2μm, 3μm, 5μm and 7μm and different orientations. Reliability tests show no impact on TSV KOZ on both FEOL and BEOL device performance. Additionally, we also performed a thinning study on the TSV wafers to characterize the impact of the wafer thinning process. We observed negligible difference between pre-thinning and post-thinning measurements and they fall within the expected wafer-to-wafer and lot-to-lot variability of the 14nm baseline process. As part of our ongoing reliability qualification for 14nm TSV reliability tests is currently being performed on these thin wafers.

Low-κ SiCOH reliability is a growing concern for integrated circuit reliability. An important consideration for product qualification involves the accurate extrapolation to the low percentile failures based on the results from a group of samples. A method is presented to determine the root cause of failure distributions amongst a group of dielectric samples using voltage ramp data. Samples' leakage current traces and breakdown voltages are compared with each other. Using this method, it was determined that the dielectric spacing variation dominates across-wafer failure, while variation of local breakdown strength affects in-chip failure.

We present a fully integrated 7nm CMOS platform featuring a 3 rd generation finFET architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology reflects an improvement of 2.8X routed logic density and >40% performance over the 14nm reference technology described in [1-3]. A full range of Vts is enabled on-chip through a unique multi-workfunction process. This enables both excellent low voltage SRAM response and highly scaled memory area simultaneously. The HD 6-T bitcell size is 0.0269um 2 . This 7nm technology is fully enabled by immersion lithography and advanced optical patterning techniques (like SAQP and SADP). However, the technology platform is also designed to leverage EUV insertion for specific multi-patterned (MP) levels for cycle time benefit and manufacturing efficiency. A complete set of foundation and complex IP is available in this advanced CMOS platform to enable both High Performance Compute (HPC) and mobile applications.

Cu barrier thickness optimization on our 90nm pitch Vx/Mx layers with porous ULK SiCOH (κ=2.55) was systematically investigated. Both via resistance and intrinsic EM performance favors thinner TaN and Ta films, however, the robustness of the plating requires thicker Ta to improve seed quality that withstand dissolution during plating. Overall, a thin TaN barrier with moderate thick Ta provides the optimum solution for performance, reliability and yield.

The time-dependent dielectric breakdown (TDDB) in on-chip interconnect stacks is one of the most critical failure mechanisms for microelectronic devices. The aggressive scaling of feature sizes, on both devices and interconnects, poses serious challenges to ensure the required product reliability. Conventional reliability tests and postmortem failure analysis provide only limited information about the physics of failure mechanisms and degradation kinetics. Therefore, it is necessary to develop new experimental approaches and procedures to study the time-dependent failure mechanisms and degradation kinetics, in particular. In this paper, comprehensive transmission electron microscopy (TEM), particularly an in situ experimental methodology, is demonstrated to investigate the TDDB degradation and failure mechanisms in Cu/low-k interconnect stacks. A dedicated “tip-to-tip” test structure is designed in the 32-nm complementary metal-oxide-semiconductor (CMOS) technology node, to restrict the failure site, and is the key basis for the in situ and ex situ TEM investigations. High-quality imaging and chemical analysis are used to identify the failure mechanism and study the kinetic process. The in situ electrical test is also integrated into the in situ TEM investigation, to provide an elevated electric field to the dielectrics. Electron tomography is utilized to characterize the directed Cu diffusion in the insulating dielectrics. These experimental approaches open a different possibility to study the TDDB failure mechanism in interconnect stacks of microelectronic products, and it could also be extended to other structures in active devices.

The indentation modulus of thin films of porous organosilicate glass with a nominal porosity content of 30% and thicknesses of 350nm, 200nm, and 46nm is determined with help of atomic force acoustic microscopy (AFAM). This scanning probe microscopy based technique provides the highest possible depth resolution. The values of the indentation modulus obtained for the 350nm and 200nm thin films were respectively 6.3GPa±0.2GPa and 7.2GPa±0.2GPa and free of the substrate influence. The sample with the thickness of 46nm was tested in four independent measurement sets. Cantilevers with two different tip radii of about 150nm and less than 50nm were applied in different force ranges to obtain a result for the indentation modulus that was free of the substrate influence. A detailed data analysis yielded value of 8.3GPa±0.4GPa for the thinnest film. The values of the indentation modulus obtained for the thin films of porous organosilicate glasses increased with the decreasing film thickness. The stiffening observed for the porous films could be explained by evolution of the pore topology as a function of the film thickness. To ensure that our results were free of the substrate influence, we analyzed the ratio of the sample deformation as well as the tip radius to the film thickness. The results obtained for the substrate parameter were compared for all the measurement series and showed, which ones could be declared as free of the substrate influence.

The impact of after level reliability of TSV has been studied with respect to FEOL (Front End of Line) and BEOL (Back End of Line) and aspects. A TSV keep out zone (KOZ) study has been done with varying gate length and width of transistor. Gate voltage (Vg) vs saturation current (Idsat) plots show that there is negligible impact on Idsat due to mechanical stress of the TSV for <; 3μm KOZ for both NFET and PFET devices fabricated with thin and thick gate-oxide dielectric. Voltage/Ramp Stress (VRS) and Constant Voltage Stress (CVS) tests were performed to analyze FEOL reliability for degradation phenomena such as Voltage Break Down (VBD), Hot Carrier Injection (HCI), and Bias Temperature stability (BTI). Test structures were designed to investigate TSV impact on the lower metal and via levels of the BEOL stack. BEOL reliability analysis for degradation phenomena such as Time Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and Stress Migration (SM) were performed to investigate any potential impact to due to TSV mechanical stress or Cu pumping effects. BEOL Our investigations showed no significant impact to FEOL or BEOL test structures due to the TSV via middle approach.

This paper proposes a methodology to determine a realistic time-dependent dielectric breakdown failure rate. The in-die constant voltage stress was performed to determine the chip level Weibull shape (βdie) and voltage acceleration factor, while a voltage ramp (Vramp) is performed in production line (inline Vramp) to determine the via-to-line and line-to-line spacing distributions. We found that for the chip population with spacing (s) smaller than 4 nm, the in-die voltage accelerations based on power-law and sqrt-V models do not lead to a significant difference in the lifetime prediction. For the chips with large spacing, the stress voltage (~20 V) is significantly higher than the operating voltage (1 V). The extrapolation using the power law results in an infinitely long lifetime, which could lead to an overoptimistic reliability prediction. In this paper, a new method is introduced for a more realistic failure rate calculation, which is the superposition of the failure rates of chips with small spacing (s <; 4 nm) and the failure rates of chips with large spacing, by using different voltage acceleration models.

Dielectric thickness impact on Time Dependent Dielectric Breakdown (TDDB) of Ultra-Low-κ (ULK) (κ=2.7) and porous ULK SiCOH (κ=2.55) was systematically investigated using Constant Current Stress (CCS) method on our 64nm pitch double patterned metal layers. Invariance of J 2 t BD suggests that the NBlock-IMD interfacial Cu diffusion is the dominant failure mechanism at stress conditions. Applying a power law dependence of J 2 t 63.2 on the physical spacing convincingly demonstrates that the critical Cu density required for breakdown depends on the dielectric thickness. By normalizing the Time to BreakDown (t BD ) according to each individual device's characteristic spacing, the β value obtained is much closer to expected intrinsic value. Results and analysis thus show that great care is needed when taking into account the impact of dielectric thickness scaling on calculating the total fail rate and on extrapolating current TDDB data to future technology generations, where much tighter BEOL pitch is likely needed.

Process sensitivity of IMD TDDB in a vertical natural capacitor (VNCAP) structure was evaluated in this paper. Among others, CMP slurry and wet clean chemical were found to have higher level of interaction impacting TDDB performance. This enables proper process optimizations, such as reduction in the Cu+ concentration on ULK top surface. Additionally, dependence of the structure was analyzed and the top metal layer is identified as the weakest link in VNCAP failure. A solution for this was described and it involves accelerated thermal cure step which successfully recovered dielectric electric strength.

The time-dependent dielectric breakdown (TDDB) in on-chip interconnect stacks is one of the most critical failure mechanisms for microelectronic devices. The aggressive scaling of feature sizes, both on devices and interconnects, leads to serious challenges to ensure the required product reliability. Standard reliability tests and post-mortem failure analysis provide only limited information about the physics of failure mechanisms and degradation kinetics. Therefore it is necessary to develop new experimental approaches and procedures to study the TDDB failure mechanisms and degradation kinetics in particular. In this paper, an in situ experimental methodology in the transmission electron microscope (TEM) is demonstrated to investigate the TDDB degradation and failure mechanisms in Cu/ULK interconnect stacks. High quality imaging and chemical analysis are used to study the kinetic process. The in situ electrical test is integrated into the TEM to provide an elevated electrical field to the dielectrics. Electron tomography is utilized to characterize the directed Cu diffusion in the insulating dielectrics. This experimental procedure opens a possibility to study the failure mechanism in interconnect stacks of microelectronic products, and it could also be extended to other structures in active devices.