The AI era is demanding ever-increasing memory capacity and bandwidth, where 3D-stacked ferroelectric memory (FeRAMs) utilizing nondestructive readout (NDRO) ferroelectric capacitors (FeCAPs) stand as a promising candidate. This work addresses NDRO sensing signal challenges in deeply scaled 3D FeRAMs using a current-mode sensing scheme, co-designed with the device architecture to overcome signal degradation due to capacitive charge sharing. By exploring gm cell design and time-differential bipolar readout, we demonstrate the feasibility of 3D stacking up to 128 FeCAPs while maintaining sub-μs access, transcending the conventional charge sharing-defined stacking limit of 64 and achieving an effective bit density of ∼ 200 Mb/mm2. Using a two-stage Miller-compensated high-GBW OTA implementation, we additionally underscore the robustness of our sensing scheme against variability in CMOS circuits, but also in bit-cell FeCAPs, such as FeCAP area variation (∼ 80%), memory window fluctuation (∼ 15 aF) and work function asymmetry (∼ 200 mV). The proposed architecture further provides a flexible design tradeoff between read speed and energy consumption, where a single-stage low-power OTA design allows read energy scaling down to ∼ 10 pJ/bit at μs-level access time. The FeCAP model is calibrated to experimental data, ensuring realistic simulation fidelity. These results offer instrumental insights into the design-technology co-optimization (DTCO) of 3D FeRAM-based storage-class memories (SCMs).

A comprehensive study on the design scaling in angstrom nodes is performed on a high-density processor core. The scaling trends foresee the degradation of BEOL routability and pin accessibility over technology nodes. In results, designs in A7 node reach −6% utilization compared to N 2 node, enlarging area by 8% from the expected level. Nevertheless, increasing M1 density with higher gear ratio (GR) is proposed to recover routability. GR $2: 1$ is shown to significantly increase utilization in A7 designs, reducing $14 {\%} / 8 {\%}$ area vs. GR 1:1/3:2 while keeping performance & power impacts within 2%. Thus, GR 2:1 is required to achieve expected area scaling for high-density designs in angstrom nodes.

Double-flip sequential CFET (sCFET) architecture enables split-gate devices and dense BM0 routing, supporting 3-track standard cells with high library efficiency. Hybrid orientation and asymmetric nanosheet widths in sCFET further optimize device-level PPA, offering scaling potential.

We model experimental NanoWire (NW) nFET I-V aging under Bias Temperature Instability (BTI) and Hot-Carrier (HC) stress using our compact physics-aware framework ComphU. We introduce a new simplified and computationally efficient approach to Distribution Function (DF) modeling applicable for short- $L_{\mathrm{g}}$ FETs and successfully lump the time- 0 variability into a limited parameter set. Our model describes experimental $\Delta V_{\text {th }}(t)$ and $\Delta I_{\text {d,on }}(t)$ traces well. Using the calibrated model, we find that $i$) the intrinsic time- $0 g_{m, \text { max }}$ is 39 % higher than the extrinsic one, ii) aging outside the calibration region is predicted reasonably, and that the BTI lifetime iii) roughly doubles for every 0.1 V reduction in the supply voltage and $i v$) increases up to $6.3 \times$ for every 0.1 V increase in $V_{\text {th, } 0}$.

We present a system-level thermal simulation framework with nanoscale transport awareness that can resolve steady state temperature maps of any circuit region of interest in cm-scale systems-on-a-chip (SOCs) with highly non-uniform power dissipation down to transistor channel detail with sub-nm resolution. Devoid of machine learning, our method requires neither neural network training nor large data storage or specialist hardware. Computing the temperature map across 100+ mm2 SOCs and executing a selective 4-stage zoom down to intra-device level typically takes less than 15 seconds on a laptop computer.

We present imecSHE, a 3-D deterministic Boltzmann transport equation (BTE) solver for computing heat generation in realistic devices. Input-power-scaled Gaussian heat-generation profiles are shown to overestimate heating in the nanosheet-FET (NSFET) by an order of magnitude. Our simulations resolve the 3-D topology of heat generation and show that lowering the carrier effective mass can significantly reduce heating. Mobility-inferred effective mass is further employed to qualitatively study the channel reorientation effect on heat generation. Along the imec roadmap A14 -> A3 scaling, p-FETs benefit the most with the heat-fraction (HF) dropping from 0.76% to 0.32%, while the n-FET HF is nearly unchanged. Finally, scaling studies identify actionable levers. Shorter channels and smaller drain size reduce heat. By providing physics-based heat-generation profiles in realistic 3-D devices instead of assumed heat sources, imecSHE enables quantitative optimization of device and process design to suppress heat generation for technology pathfinding.

Technology nodes of the Angstrom era are facing scaling limitations that exacerbate the already challenging technology constraints. Technology boosters and innovative materials could help close the gaps, but they come with costly integration solutions. A key challenge is to determine the actual impact of the BEOL and, more specifically, to identify which BEOL layer constrains the performance targets of current or future technology nodes. Identifying the main bottleneck is essential for guiding technology research in the right direction. This paper introduces Critical Path Modeling (CPM), an analytical methodology to assess the impact of resistance (R) and capacitance (C) on the block-level performance of physically implemented digital designs. Elmore delay is computed from the detailed net topology to evaluate the effects of interconnect R and C, as well as pin capacitance, on interconnect delay. The impacts on cell delay are assessed by linearizing the non-linear delay model that characterizes cell timing. CPM results are derived from the physical implementation of diverse digital designs, ranging from 15k to 2.5M logic cells, targeting multiple optimization objectives across imec’s N2, A14, and A7 technology nodes. Compared to classical Static Timing Analysis (STA) sensitivity analyses, Design-Technology Co-Optimization (DTCO) loops are accelerated by at least 12×, with an accuracy loss of less than 0.7 percent.

We propose an extended version of the design technology co-optimization (DTCO) flow, which-in contrast to the commonly acknowledged DTCO paradigm relying on the power-performance-area (PPA) metric-considers reliability as a tangible parameter, thereby leading to a concept of PPAR ("R" stands for "reliability"). As a demonstration of this concept, we carry out a comprehensive reliability analysis of future imec nanosheet field-effect-transistor (NSFET) logic nodes with gate lengths scaling from 15 to 10 nm. Our focus is placed on hot-carrier degradation (HCD) and bias temperature instability (BTI) modeling over stress time of up to ten years. For an accurate description of HCD, we employ our technology computer-aided design (TCAD)-based HCD model, which relies on the modeling of carrier transport. A thorough analysis of the electric field and carrier concentration shows that both quantities peak at the rounded nanosheet (NS) corners, which enhances HCD; the most severe HCD occurs in NSFETs with the smallest corner radii. BTI simulations-conducted with the nonradiative multiphonon (NMP) model-exhibit a similar behavior: BTI becomes stronger as the NS corners become sharper. Overall, all degradation metrics decrease monotonically as the NS corner radius increases. These results indicate that field-effect transistor (FET) architectures with larger NS corner radii provide improved robustness against both HCD and BTI, and should be favored for future technology nodes. Our concept allows considering the reliability of future (not yet fabricated) transistor nodes, thereby making reliability an essential DTCO ingredient.

As logic scaling enters the angstrom era, vertically stacked complementary field-effect transistors (CFETs) based on atomically thin two-dimensional (2D) semiconductors offer a potential route to extend device scaling beyond the A2 node. Here, we develop an A2-oriented 2D CFET integration flow with a CPP of 36 nm and Lg of 10 nm and present initial demonstrations of several key process modules. Despite their atomically thin channels, 2D GAA CFETs do not provide a contacted poly pitch scaling advantage over Si GAA CFETs at the A2 node, because contact formation constraints impose a similar minimum CPP of 36 nm. We also combine a critical assessment with a multiscale power-performance-area (PPA) evaluation framework spanning quantum transport simulations, compact-model generation, A2-targeted 2D CFET gate-all-around (GAA) integration-flow definition, parasitic extraction and circuit-level benchmarking. Our analysis, however, shows that the expected benefits of 2D GAA CFETs are strongly constrained by non-idealities, in particular high contact resistance and dominant layout-induced parasitic capacitances. Although architectural optimization can improve the Ieff/Ceff ratio, the associated rise in absolute capacitance limits circuit-level gains. Meaningful progress will require co-optimization of contacts, transport and parasitics, together with 2D-specific CFET architectures.

We evaluate block-level power-performance-area benefits of backside power delivery networks (BSPDNs) in power switched designs, using Through Silicon Via in the Middle of Line (TSVM) in an N2 (2nm) nanosheet technology. We use an industrial processor design, representative of mobile computing, to compare the BSPDN implementations to traditional frontside power delivery networks (FSPDNs), in both always-on and power switched implementations. BSPDNs benefit both domains, reducing IR drop and enabling smaller block-level area at iso-performance conditions. FSPDNs consume significant routing resources to ensure an acceptable IR drop, especially in power switched designs employing local PDN assists to achieve the target IR drop. Moving PDN to the backside frees up resources, resulting in smaller area for both power switched (-14%) and always-on (17%) domains. BSPDN enables the use of $2 \times$ fewer power switches, achieving an additional 9% area reduction.

This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.

Complementary FET (CFET) is a promising device architecture that proceeds the CMOS scaling during the post-nanosheet device era. Among several CFET variants, Double-Row (DR) CFET further enables 15% track height scaling on standard cells, by sharing a middle row of vias, while sustaining an optimized Middle-Of-Line (MOL) process complexity. In this study, half-height double-row (hDR) CFET is proposed as a highly practical and impactful design style to overcome the cell and block level limitations of DR CFET architecture. First, hDR CFET introduces a high flexibility on standard cell layout design with significant area optimization. Secondly, hDR cell insertion in the backend physical design flow further optimizes the cell placement, and recovers block level area scaling to match the cell height scaling. Results on A7 CFET technology library show area reduction up to 50% on standard cell layouts. Moreover, block level PnR results after enabling only 6 types of hDR cells in standard cell library show 10% of area scaling on ARM Cortex-M0 32-bit core at 90% utilization, proving the strength of the concept. Finally, 14% of block level area scaling is further projected for an enriched standard cell library with an extended set of hDR cells.

Outer wall forksheet device architecture enables further scaling of gate-all-around (GAA) technologies, while maintaining full channel control through Omega-gate, and full $\mathrm{s} / \mathrm{d}$ stress efficacy. The presented wall-last approach allows for a continuous crystal template during epi growth, enabling full channel stress. Furthermore, the wider wall reduces process complexity and enables omega gate through wall etch back, effectively creating a GAA channel, increasing electrostatic control, and boosting on-current by 27 % compared to tri-gate forksheet architecture.

This work explores the cross-node scaling potential of SOT-MRAM for last-level caches (LLCs) under heterogeneous system scaling paradigm. We perform extensive design-technology co-optimization (DTCO) exercises to evaluate the bitcell footprint for different cell configurations at a representative 7 nm technology and to assess their implications on read and write power-performance. We crucially identify the MTJ routing struggle in conventional two-transistor one-resistor (2T1R) SOT-MRAMs as the primary bitcell area scaling challenge and propose to use BEOL read selectors (BEOL RSs) that enable (10%-40%) bitcell area reduction and eventually match sub-N3 SRAM. On writability, we affirm that BEOL RS-based bitcells could meet the required SOT switching current, provided the magnetic free layer properties be engineered in line with LLC-specific, (0.1-100) s retention targets. This is particularly to attribute to their: 1) more available Si fins for write transistor (WRT) and 2) lower bitline resistance at reduced cell width. We nevertheless underscore the read tradeoff associated with BEOL RSs, with the low-drive IGZO-FET selector sacrificing the latency up to (3-5) ns and the imperfectly rectifying diode selectors suffering (2.5-5) x energy cost relative to 2T1R. This article thus highlights the realistic prospects and hurdles of BEOL RSs toward holistic power-performance-area (PPA) scaling of SOT-MRAM.

Advancements in 2.5D and 3D technology have emerged as breakthroughs within the realm of semiconductor innovation with enhanced performance, efficiency and miniaturization of semiconductor devices. Given the substantial space occupied by SRAM in modern day system-on-chips (SoCs), 3D SRAM promises footprint reduction and enhanced chip performance. Face-to-face (F2F) hybrid bonding is extensively used to bond two or more operational silicon chips to get 3D stacked chips. However, these bond pads have significantly higher pitch when compared with the SRAM bit-cell dimensions and hence the data bandwidth is limited by the bond pitch of the linearly arranged hybrid bond pads. This work demonstrates a staggered pillar configuration to overcome the 3D F2F bond pad pitch limit and hence increasing the bandwidth of the 3D SRAM macro significantly. The 3D SRAM macro with staggered pillar configuration achieves 2x, 4x and 7x improvement in the bandwidth for 400 nm, 700 nm and 1 mu m bond pad pitches, respectively, compared to non-staggered 3D configuration in A14 nanosheet technology.

We investigate electron transport in multilayer 2H-transition metal dichalcogenides (2H-TMDs), using WS2 as a representative material due to its prototypical band and phonon structure shared across the 2H-TMD family. Employing first-principles calculations, we incorporate full-band electronic structures and electron–phonon matrix elements within the Boltzmann transport equation framework to study both low-field mobility and high-field velocity characteristics in monolayer (ML), bilayer (BL), and trilayer (TL) WS2. A key focus of this work is the role of multivalley dynamics, particularly the influence of K–Q valley separation (EKQ) on transport behavior. We show that mobility is highly sensitive to EKQ, with larger separations favoring K valley occupation and enhancing mobility due to reduced intervalley scattering and lower effective mass. As the number of layers increases, EKQ decreases, leading to mobility degradation, although TL exhibits partial recovery due to contributions from additional subbands. We further demonstrate that valley engineering—e.g., tuning EKQ via lattice modification—can significantly improve mobility. At high carrier concentrations and high fields, however, both valleys are populated regardless of separation, resulting in reduced mobility and saturation velocity. These findings provide critical insights into the design of high-performance electronic devices based on layered TMDs.

This paper addresses several aspects of clock net distribution in the context of sub-2nm CMOS ICs, where power delivery networks have been enabled to move to the back side of the chip (BSPDN). Moving the mainstream power delivery network to the back side significantly reduces the self-capacitance of the top back-end-of-line (BEOL) metal layers (Mz). This benefits the clock energy consumption (reduced down to 10% of FSPDN+FS-Mz clock). However, clock nets routed on Mz layer with no power supply around, make the clock very noisy. In this paper, we show that in case of BSPDN, a set of correlated aggressors, can couple to the clock signal and contribute a data- dependent jitter of up to 40% of the clock period, due to an unshielded or poorly shielded clock. We also show that due to undefined return paths, the self and mutual inductive noise can be a potential cross talk mechanism degrading the clock quality further, even with a shielded clock in place. This gets worse for 3D integration specially in F2F (Face to Face) bonding option. We also propose that moving a majority of clock to the back side along with the BSPDN, can be a better alternative than only providing shielding on the front side. Energy consumed in BSPDN+BS-Mz is just similar to 15% of the energy compared to FSPDN+FS-Mz clock and a much improved signal integrity.

We evaluate block-level power-performance-area (PPA) tradeoffs of two backside power (BSPDN) options: Through Silicon Via in the Middle of Line (TSVM) and Backside Contact (BSC) in an A10 (10A) nanosheet technology node. The benchmarking was conducted for high-performance designs in both high-performance and high-density technology scenarios taking the traditional frontside power option as the baseline. HP technology clearly benefits most since its dense PDN consumes a lot of metal routing resources on the frontside to keep an acceptable IR-drop. Introducing BSPDN frees up those metals for more efficient signal routing, resulting in 19% smaller area (8% for HD). Continued standard cell scaling by means of BSC translates into a further -25% core area, with only the densest 4.5T HD results showing signs of congestion at high frequencies.

In this paper, we make a thermal-aware block-level PPA comparison study for nanosheet transistors (NSFET) and complementary field effect transistors (CFET), expected to be used in future Angstrom nodes, namely A10 and AS respectively. We report block-level scaling results from AI0 to AS node on an open-source many-core architecture: 2.5% increase in F max , 25% reduction in power, 27% reduction in energy per cycle, achieved with 35% area reduction and a consequent increase in power density by 15% under nominal 0.7V/2SC. The PPA analysis methodology has been augmented with a fast package-level thermal simulator to enable early self-consistent thermal estimation that accounts for exponential leakage power increase with temperature, which is important for dynamic thermal management (DTM) applications. The analysis reveals a reduction of 64mV in Vdd and 10% in frequency required for A5 node to maintain same T j,max as Al 0 node operating at 0. 7V, still resulting in a 40% gain in system throughput.

Beyond FinFET device nodes, nanosheet is the next transistor architecture in CMOS scaling roadmaps. On top of the newer device architectures and materials, several other CMOS scaling boosters are being considered, and can help in further to improve the power, performance and area scaling. Backside power delivery network (BSPDN) is one of the promising scaling boosters, e.g. it disengages metal routing resources from the frontside, resulting in a lower routing congestion. Hence, the BSPDN booster paves the way for higher frequency and lower area footprint. However, ad-hoc standard cell design and optimization is required to connect the BSPDN network to the logic devices located in the front-end-of-line (FEOL). In this study, the implementation of different connection options to the BSPDN are studied in imec's A14 nanosheet node: i.e. Through Silicon Via in the Middle of Line (TSVM), buried power rail (BPR) and direct backside contact (BSC). The different implications on standard cell design, as cell track height, routing and main process challenges are then compared to the classic frontside power delivery option. Finally, high-density (HD) standard cell libraries are implemented and characterized. Normalized area and delay comparisons at the library-level are presented. Area gains can rise up to 25% in case of BSC BSPDN option. Furthermore, maximum delay gains can vary up to 20% depending on standard cell type.