The negative bias temperature instability (NBTI) of nanoscaled Si0.45Ge0.55 pFETs with different thicknesses of the Si passivation layer (cap) is studied. Individual discharge events are detected in the measured threshold voltage shift (ΔVth) relaxation traces, with exponentially distributed step heights. The use of a thinner Si cap is shown to reduce both the average number of charge/discharge events and the average ΔVth step height. To qualitatively explain the experimental observations, a simple model including a defect band in the dielectric is proposed.

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III–V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al2O3/GaSb interface have been studied by in situ deposition of an Al2O3 high-κ gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C–V with relatively low Dit along the bandgap, these results point out an efficient electrical passivation of the Al2O3/GaSb interface.

An analysis of dopant diffusion and defects in SiGe-channel Quantum Well (QW) with Laser annealing using an atomistic KMC approach are shown. Thin SiGe layer with high Ge content for SiGe-channel QW has an impact on implantation damage and Boron-Transient Enhanced Diffusion (TED) suppression, and defect evolution. KMC shows that As-pocket in SiGe-channel pFET shows enhanced diffusion toward SiGe-channel and higher As concentration in SiGe-channel. The difference of pocket diffusion is one of possible reason for the higher Vth mismatch for SiGe-channel with As pocket than for Si-channel.

Over the last years there has been lots of interest in the use of germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility has attracted lots of attention for its application in advanced pMOS devices. Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS devices beyond 14 nm node technology.

The introduction of SiGe channel pMOSFETs for high mobility devices is expected to enhance the impact ionization phenomenon, making it necessary to study Hot Carrier (HC) degradation also for the p-channel MOSFET reliability. The study of pure HC effects on pMOSFETs is complicated due to the mixing with Negative Bias Temperature Instability (NBTI). In the first part of this work the interaction of the two degradation mechanisms is studied thoroughly on Si devices with the extended measure-stress-measure (eMSM) technique which is capable of capturing both the charge trapping and the interface state creation components of the degradation. HC degradation is shown to enhance interface state creation, while eventually reducing the charge trapping w.r.t. standard NBTI. These experimental results are supported by MEDICI simulations. The second part of the paper focuses on the HC reliability of Si0.45Ge0.55 pMOSFETs. These devices show enhanced degradation w.r.t. their Si counterparts, confirming the importance of studying HC effects for the reliability of this technology. Nevertheless, the SiGe device reliability can be enhanced when reducing the thickness of the Si cap.

In this work, we demonstrate for the first time 3D-carrier profiling in FinFETs with nm-spatial resolution using SSRM. The results provide information on gate underlap, dopant conformality, source/drain doping profiles. The 3D-carrier profiles as extracted for two different device approaches (extensions vs. extension-less) are conclusive in demonstrating the differences in device performance and are consistent with first order 3D-simulations.

The pronounced high interfacial densities of states (Dit) commonly observed around the midgap energy of dielectric/GaAs interfaces are generally considered the culprit responsible for the poor electrical performance of the corresponding inversion-channel metal-oxide-semiconductor field-effect-transistors. In this work, comprehensive Dit spectra as the function of energy [Dit(E)] inside the In0.2Ga0.8As band gap were constructed by using the quasistatic capacitance-voltage and the temperature-dependent conductance method on n- and p-type ultrahigh vacuum (UHV)-Ga2O3(Gd2O3)/In0.2Ga0.8As and atomic-layer-deposited (ALD)-Al2O3/In0.2Ga0.8As metal-oxide-semiconductor capacitors. Unlike the ALD-Al2O3/In0.2Ga0.8As interface giving a Dit spectrum with a high midgap Dit peak, the UHV-Ga2O3(Gd2O3)/In0.2Ga0.8As interface shows a Dit spectrum that monotonically decreases from the valence band to the conduction band with no discernible midgap peak.

This paper presents a novel strategy to achieve conformal FINFET extension doping with low tilt-angle beam-line ion implantation. The process relies on the self-aligned cap layer formation exclusively on top of the FIN to tune doping levels in this particular area by partial dopant trapping. The conformality itself is evaluated for n- and p-type dopants by a novel extraction method applied to FIN resistor test structures. Furthermore, the process was integrated into a full NMOS device flow and compared to a highly tilted and more conformal As implant condition.

Publisher regrets that this article is has already been published in another journal. The duplicate article has therefore been withdrawn.

We will present the defect density at In0.53Ga0.47As and InP interfaces with ALD Al2O3 derived by use of the conductance method and from simulation of low frequency CV-curves. Consequences of the interface state distribution for MOS transistor device operation will be highlighted through 1-dimensional electrostatic simulations. The simulation results will be compared as much as possible to different state-of-the-art transistor results presented in literature.

This work focuses on the analytical description of junction leakage in the low-voltage range (<1V) of short-channel HDD junctions, where the dominant contribution comes from the TAT regime. Starting from diodes with varying area/perimeter ratios, the area leakage contribution to the total junction leakage is experimentally determined for junctions with varying halo conditions and threading dislocation density (TDD). On the other hand, the Synopsys software of Sentaurus-Process and MEDICI was used to verify the electrical models.

The change of the energy profile of the initially present HfSiO defects in nMOSFETs after V th adjustment by As and Ar implantations is investigated. A fundamental correlation between the density of energetically deep traps and the initial V th is revealed, suggesting that the negative bulk charge in HfSiO controls the V th .

An analysis of pocket profile deactivation and its impact on Vth variation for Laser annealed devices using an atomistic kinetic Monte Carlo (KMC) approach are shown. The Carbon co-implant impacts on pFET extension/pocket are also modeled using an atomistic KMC. KMC clarified that although B-pocket in nFET shows significant deactivation, As-pocket in pFET does not show deactivation with thermal budget scaling. pFET device shows smaller thermal budget scaling dependence of Vt mismatch than that of nFET. The difference of pocket deactivation is one of important reason for higher Vth mismatch for nFET than for pFET.

Atom probe tomography (APT) in conjunction with scanning spreading resistance microscopy (SSRM) is demonstrated for the first time to profile dopant and carrier distributions in FinFET-based devices with sub-nanometer resolution. These two techniques together provide information on the degree of conformality, the dose retention and the dopant activation. These results are also compared with a methodology involving secondary ion mass spectrometry (SIMS). Ion implantation for increased conformality of source/drain extensions is demonstrated for tilted implants, which clearly leads to improved device performance.

6Å EOT Si0.45Ge0.55 pFETs with 10 year lifetime at operating conditions (VDD=1V) are demonstrated. Ultra-thin EOT is achieved by interfacial layer (IL) scavenging. Negative Bias Temperature Instability (NBTI) is alleviated using a high Ge fraction, a thick SiGe quantum well (QW) and a thin Si cap. Hot Carrier Injection (HCI) and Time Dependent Dielectric Breakdown (TDDB) are shown also to not constitute a showstopper for optimized SiGe devices.