Editor's note: Assurance of functional safety is a critical component of automotive SoC design, specifically in the context of autonomous driving and advanced driver assistance. This tutorial, written based on the authors' strong industry experience, outlines the key challenges associated with functional safety and practices as well as standards to address them.-Swarup Bhunia, Case Western Reserve University.

This article points out that the fundamental problem of platform verification is incompleteness of the test plan and proposes an unsupervised learning approach to augment the test plan.-Magdy Abadir, Helic Inc.

Security verification relies on using direct tests manually prepared. Test preparation often requires intensive efforts from experts with in-depth domain knowledge. This work presents an approach to learn from direct tests written by an expert. After the learning, the learned model acts as a surrogate for the expert to produce new tests. The learning software comprises a database for accumulating and sharing security verification knowledge. The learning approach uses process discovery to build an upper-bound model and continuously adds constraints to refine it. We demonstrate the feasibility and effectiveness of the learning approach in a commercial SoC verification environment.

Verification has been one of the major bottlenecks in integrated circuit design process, which is exacerbated by the sheering design complexities nowadays. The increased design size is only one dimension of the growing complexities. Recent System-on-Chips (SoC) often feature multiple heterogeneous embedded processors and accelerators. While the heterogeneous architecture is more power efficient, it adds verification complexities of the hardware/software interaction and interconnect coherency. It is common that tens or hundreds of IP blocks, among which analog IPs occupy an increasing portion, are integrated into a single chip. Moreover, the growing market shares of devices for Internet-of-Things (IoT) and automotive applications have signified the requirements for verifying security and safety, which adds new dimensions to the complexities. As a result, the industry has encountered emerging challenges for correctly verifying increasingly complex SoCs in a timely manner, which create the “verification gap.” This special issue is devoted to address the verification challenges, the needs for advanced verification technologies to close the gap, and the state-of-the-art solutions.

A modern automotive design contains over a hundred microprocessors, several cyber-physical modules, connectivity to a variety of networks, and several hundred megabytes of software. The future is anticipated to see an even sharper rise in complexity of this electronics, with the imminence of driverless vehicles, the potential of connected automobiles within a few years, and work towards seamless integration of automobiles with smart cities and infrastructure systems. Security is a fundamental challenge in the design of automotive systems. Unfortunately, security considerations in automotive systems are complicated by two factors: (1) need for real-time mitigation against in-field threats; and (2) in-field configurability and extensibility of security features. This paper examines the trade-offs between security countermeasures, real-time requirements, and in-field configurability needs for modern automotive systems. We discuss the current state of the practice in automotive security architecture, as well as gaps and challenges that need to be addressed for a viable security solution in future.

Feature selection is essential to rule learning in the context of functional verification. In practice today, features are selected manually and the selection requires domain knowledge. In contrast, this work proposes using automatic feature extraction from design documents as a viable approach to support rule learning. To demonstrate its effectiveness, document-extracted features are employed to learn the rules for covering a set of assertions based on a commercial SoC. Experiments show that 100%-accurate rules can be obtained for more than 70% of the assertions.

This paper provides a tutorial overview of the state-of-the-art in verification of complex and heterogeneous Systems-on-Chip. The authors discuss current industrial trends and key research challenges.

Security is a critical challenge for modern embedded, mobile, and IoT devices. One the one hand, these devices contain sensitive assets that must be protected from unauthorized access. On the other hand, high design complexity, aggressive time-to-market, and a complex, global supply-chain provide numerous opportunities for introduction of errors, vulnerabilities, and security backdoors that can be exploited on-field to compromise the device. In this paper we look at some of the security challenges in this era: questions on the root of trust and certification challenges in mobile and embedded devices, conflicts and trade-offs between security and functional debug, and vulnerability results from widespread application of electronic design automation (EDA) tools for system synthesis.

The emergence of Internet-of-Things has imposed more stringent security requirements on SoC devices. Basic security requirements include confidentiality and integrity, which imply less observability and controllability of the SoC from the outside world. On the other hand, observability and controllability are essential to SoC debug activities. Without bearing in mind the conflicting nature of security and debug requirements, sensitive information on the SoC can be compromised due to vulnerabilities introduced by debug circuitry. This paper reviews the security hazards that can be induced by SoC debug components and discusses the challenges of striking a balance between the security and debug requirements. We review the current practice, and provide an industrial perspective on how this problem can be better solved in the future.

This paper investigates how data mining can be applied in functional debug, which is formulated as the problem of explaining a functional simulation error based on human-understandable machine states. We present a rule discovery methodology comprising two steps. The first step selects relevant state variables for constructing the mining dataset. The second step applies rule learning to extract rules that differentiates the tests that excite error behavior from those that do not. We explain the dependency of the second step on the first step and considerations for implementing the methodology in practice. Application of the proposed methodology is illustrated through experiments conducted on a recent commercial SoC design.

Novel tests are important in simulation-based functional verification because they provide coverage of difficult-to-verify corners. In this work, we did an experimental study on how to learn from the novel tests to help improve structural coverage in functional verification. A feature-based learning methodology is proposed to diagnose the reasons why a novel test contributes to coverage of a target block. The extracted rules can be used as constraints to improve test generation. Our experiments were conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. In one case, we improved the toggle coverage of a block in load store unit to 100%, which was otherwise difficult without learning.

Along with the shrinking CMOS process and rapid design scaling, both Iddq values and their variation of chips increase. As a result, the defect leakages become less significant when compared to the full-chip currents, making them more in-distinguishable for traditional Iddq diagnosis. Therefore, in this paper, a new approach called σ-Iddq diagnosis is proposed for reinterpreting original data and diagnosing failing chips, intelligently. The overall flow consists of two key components, (1) σ-Iddq transformation and (2) defect-syndrome matching: σ-Iddq transformation first manifests defect leakages by excluding both the process-variation and design-scaling impacts. Later, defect-syndrome matching applies data mining with a pre-built library to identify types and locations of defects on the fly. Experimental results show that an average of 93.68% accuracy with a resolution of 1.75 defect suspects can be achieved on ISCAS'89 and IWLS'05 benchmark circuits using a 45nm technology, demonstrating the effectiveness of σ-Iddq diagnosis.

introduction Share on Introduction to special section on verification challenges in the concurrent world Authors: Sandip Ray University of Texas at Austin, TX University of Texas at Austin, TXView Profile , Jayanta Bhadra Freescale Semiconductor Inc., Austin, TX Freescale Semiconductor Inc., Austin, TXView Profile , Magdy S. Abadir Freescale Semiconductor Inc., Austin, TX Freescale Semiconductor Inc., Austin, TXView Profile , Li-C. Wang University of California at Santa Barbara, CA University of California at Santa Barbara, CAView Profile , Aarti Gupta NEC Laboratories America, Inc., Princeton, NJ NEC Laboratories America, Inc., Princeton, NJView Profile Authors Info & Claims ACM Transactions on Design Automation of Electronic SystemsVolume 17Issue 3June 2012 Article No.: 19pp 1–3https://doi.org/10.1145/2209291.2209292Published:05 July 2012Publication History 0citation172DownloadsMetricsTotal Citations0Total Downloads172Last 12 Months1Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my Alerts New Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Novel test detection is an approach to improve simulation efficiency by selecting novel tests before their application [1]. Techniques have been proposed to apply the approach in the context of processor verification [2]. This work reports our experience in applying the approach to verifying a commercial processor. Our objectives are threefold: to implement the approach in a practical setting, to assess its effectiveness and to understand its challenges in practical application. The experiments are conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. By focusing on the complex fixed-point unit, the results show up to 96% saving in simulation time. The main limitation of the implementation is discussed based on the load-store unit with initial promising results to show how to overcome the limitation.

Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named σ-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that σ-Iddq testing achieves a higher classification accuracy in a 45 nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.