Two types of electron traps, donor-like and acceptor-like, are created in the gate oxide of metal-oxide-semiconductor capacitors by Fowler–Nordheim electron injections. Electrical properties (areal density, capture cross-section, centroid) of each type of trap are determined by using the avalanche electron injection method and by combining capacitance–voltage and current–voltage measurements. These properties are measured with regard to the Fowler–Nordheim fluence up to breakdown and for both injection modes (electrons injected either from the gate or from the substrate of capacitors).

In this paper it is investigated the influence of two polycide processes using WSi2 chemical vapor deposition (CVD) or TaSi2 deposition by sputtering on the integrity of wet and nitrided tunnel oxides (tox= 6.6 nm) used in Electrical Erasable Programmable Read Only Memory (EEPROM) under negative Fowler Nordheim electron injection (FNEI). It was confirmed that the nitridation reduces the generation rates of defects created by FNEI (interface states, neutral traps, positive and negative charges) and the stress induced leakage current (SILC).This reduction is more pronounced when TaSi2 is used rather than WSi2. In sputtering TaSi2 process compared to the CVD WSi2 one, it was observed : (i) - the generation of positive charges and the SILC are higher while the generation rates of interface states and negative charges are smaller ; (ii) - the generation rate of neutral traps is higher in wet oxide while it is smaller in nitrided oxides. Whatever the polycide process, the generation of the different types of defects created by FNEI is reduced by increasing the nitridation temperature while the SILC is increased.

In this work, we give some insights on the charging and discharging properties of electron traps created in gate oxide by homogeneous electron injection with the aim at further relating them to breakdown. We present a new procedure for determining the electrical properties of these traps. A model based on trap to band tunneling gives an estimation of their energy levels in the oxide gap.

The electron traps created in the gate oxide of metal oxide semiconductor devices under irradiation or electric stress such as injection of hot carriers or Fowler-Nordheim electron injection (FNEI) degrade the reliability of integrated circuits and contribute to oxide breakdown. The areal density, capture cross-section and centroid of each type of electron trap and their variation with the FNEI fluence are determined using avalanche electron injection (AEI) and combining midgap voltage (VMG) and negative Fowler-Nordheim voltage (VFN−) measurements.

A new procedure to analyze the oxide space charge created during a Fowler-Nordheim electron injection in metal-oxidesemiconductor devices is presented. This procedure was used to study the evolution of the centroid and the areal density relative to each component of the space charge with the electric field applied during the injection. The occupation probabilities of donor and acceptor like traps created in the oxide during stress are also determined.

A procedure to identify the different components of the oxide space charge created during a Fowler–Nordheim electron injection in metal–oxide–semiconductor capacitors is presented. This procedure is very simple and based on the study of the space-charge relaxation behavior depending on the conditions of polarization and temperature. A model, based on slow states, trapped holes, and fixed charges, is proposed to explain the reversible and irreversible behaviors observed. Their effective numbers per unit area can be evaluated. This procedure is used to compare the influence of different processes on the oxide resistance to electron injections.

Polysilicon diodes were designed for smart power applications (temperature sensors, clamping diodes and rectifiers). Their I-V characteristics are analysed using an adaptation of Greve's model. An optimum P doping level is studied to realise the three applications.

The experiments confirm that the charge to breakdown QBD, often used for oxide monitoring, is closely related to the positive space charge formed in the bulk of the oxide layer during electron injections. The results are justified by assuming that breakdown occurs when a critical net and effective number of charges per unit area, NC equals 5 1012 cm-2, is reached in SiO2 layers. An interpretation of breakdown induced by a positive charge is proposed, based on the polarization/relaxation process previously used to explain the electron charge induced breakdown process.

The deposition of polysilicide layers can contribute to the generation of defects in gate or tunnel oxides which can have a detrimental influence on the reliability of non-volatile memories. Two processes of WSi2 deposition were studied. The charge and the interface state densities created by Fowler-Nordheim electron injections in the gate oxide, the charge before intrinsic breakdown and the programming window degradation after erase/write cycles of EEPROM were compared. The three types of tests are well correlated.

The resistances of dry and dry/wet/dry gate oxides to Fowler-Nordheim injections are compared. Two types of test MOS capacitors were used in order to verify whether a simplified process can lead to reliable results. A dry/wet/dry oxide exhibits higher injected charge to intrinsic breakdown and smaller density of net effective trapped charge than a dry oxide does. The interface state generation rates are identical for both oxides. The improvement is attributed to higher electron trapping in dry/wet/dry oxide.

In this paper, we show that the minority-carrier diffusion length in the neutral region of MOS capacitors can be measured using some refinements to the original method given by D.K. Schroder [2] even at temperatures for which the leakage current is not exclusively due to the diffusion current. This is the case at the temperature used for the test of DRAM refresh time (80–85°C). For this temperature, we have verified that the MOS capacitor holding time is a linear function of the minority carrier diffusion length.

Coupling between the front and back interfaces of gate-controlled diodes fabricated on thin-film silicon-on-insulator (SOI) structures is investigated. Lim and Fossum's model has been modified to take into account the influence of the reverse bias, V-R, applied to the diode junction. This model is verified by capacitance, leakage current and charge pumping measurements performed by varying the front and back gate voltage as well as V-R.The study demonstrates that the intensity of the interface coupling depends on the thicknesses of the gate and buried oxides, SOI layer thickness, and dopings N-1 and N-2 near the two interfaces. Appropriate methods are used to extract these parameters.

Different methods using the relationship between surface potential ΨS and gate bias VG in metal-oxide-semiconductor (MOS) capacitors have been compared. These methods can be applied even if the doping profile is very abrupt and the interface state density very high. The shifts of midgap, flatband, and threshold voltages, observed after Fowler–Nordheim electron injection, and deduced from the various ΨS(VG) relationships obtained by these different methods, are in good agreement. These shifts give the number of effective oxide trapped charges (Nox) per unit area and acceptor-like and donor-like interface states (NSSA and NSSD) which are created during the electron injection. We reveal that the number of positive charges created in the gate oxide, unlike the number of generated interface states, strongly depends on the position of the post-metallization annealing step in the process. After relaxation of the stressed MOS capacitors, most of the generated positive charges can be attributed, in the MOS capacitors studied, to hydrogen-related species. It seems that the interface states are essentially created by the recombination of holes generated by electron impact.

AbstractWe have studied the contribution of the gate‐to‐drain overlap on the hot‐carrier induced leakage current of an NMOSFET used as gate‐controlled diode (GCD) after stress. The experimental GCD characteristic is compared to the model obtained by a home‐modified version of MINIMOS. We have introduced an arbitrary or calculated profile of interface states and charges created by hot electrons (models given by C. Hu and P. Roblin, respectively) in order to calculate by fitting their spatial distributions. We have studied also the influence of stress conditions on simulated GCD characteristics.

The degradation of a MOSFET after a stress is studied through the variation with the gate bias of the leakage current measured when the drain and source are short circuited (GCD characteristics). We have shown that it is a very sensitive method of diagnosis for the hot-carrier induced creation of interface states and charges. This method is easier to interpret than the usual charge pumping method.We have observed different types of GCD characteristics after a stress with one or two humps and with small or high tunneling currents for negative and even positive gate bias. Up to now, we have simulated the spatial distributions of interface states (or related interfacial generation velocities) and charges along the interface by only considering the impact or trapping of hot-electrons using the models given respectively by C.Hu and P.Roblin for the creation of interface states and charges. The distributions of the carriers and the electric field during a stress are given by MINIMOS.We have introduced the calculated profile of interface states and charges created by hot-electrons in a home-modified version of MINIMOS in order to calculate the interfacial generation current using the classical SHR statistic. We have effectively verified experimentally and theoretically that this current is the main component of the leakage current for the studied transistors. We have obtained simulated GCD characteristics which are in qualitative agreement with the different GCD experimental characteristics.

Electron injection at high field and moderate fluence into the gate oxide of P-channel metal–oxide–semiconductor transistors creates net positive charges and related interfacial states as it has often been reported. A threshold electric field at around 7.2 MV/cm is found for the generation of positive charges. For this same oxide field the interfacial state density increases abruptly. For an average oxide field in the 8–9-MV/cm range, the densities of positive charges and interfacial states increase linearly with the fluence for F<1016 e/cm2 and saturate for F≳1017 e/cm2. The positive charge density is more important near the channel edges. The interfacial state density seems to be homogeneously distributed along the channel. The density of electron traps is negligible for the studied dry gate oxide except in the overlaps above drain and source and in some cases near the channel edges. The negative space charge, resulting from electron trapping in these regions, reduces the length of the electron injection and in some cases the surface of the channel which contributes to the charge pumping current. Two types of relaxation have been observed.

The leakage and charge pumping currents are measured in gate-controlled MOS p-i-n diodes fabricated on thin SIMOX substrates. The efficiency of either technique as well as their complementary features are analyzed for various experimental conditions. The interface properties of device-grade SIMOX wafers are characterized and shown to be compatible with VLSI requirements. Special interface coupling effects, which occur only in fully depleted SOI devices and modify the conventional signature of charge pumping and leakage current, are thoroughly investigated.

A novel method of characterization of the micronic MOSFET degradation due to hot-carriers is proposed. It consists on the analysis of the leakage current variation with gate bias of the transistors studied as gate controlled diodes (GCD) by short circuiting the source and the drain. The GCD characteristics are plotted before and after stress. We show that the proposed method is considerably more sensitive than the usual methods which consist in the measurements of the threshold voltage, the transconductance or the subthreshold swing before and after stress. By comparison with the charge pumping method, the proposed method shows that hot-carriers create not only oxide charges and interface states but also bulk traps near the drain. Our method confirm that degradation caused by a given drain bias saturates after a certain lapse of time depending on the applied gate bias. We have observed, after a stress, a slight relaxation of the defects which are created by hot-carriers. The density of these defects are not always maximum for a stress V(GS) = V(DS)/2 as it is currently admitted [1].

Une nouvelle methode de caracterisation du vieillissement des transistors microniques et submicroniques est proposee. Elle est basee sur l'analyse de la variation du courant de fuite en fonction de la polarisation grille des transistors etudies comme des diodes controlees par grille en reliant la source et le drain. Les caracteristiques DCG sont relevees avant et apres l'operation de vieillissement qui consiste a appliquer une polarisation drain VDS et une polarisation grille VGS, par rapport a la source, pendant un temps plus ou moins long (contrainte). Nous montrons que cette methode est considerablement plus sensible que les methodes usuelles qui consistent a suivre l'evolution de la tension de seuil VTO, de la transductance gm ou de la pente S en regime d'inversion faible. Par rapport a la methode de pompage de charge [2-4], elle presente l'avantage de reveler que les electrons chauds creent non seulement des charges dans l'oxyde et des etats d'interface mais aussi des defauts volumiques au voisinage du drain. La methode proposee confirme que la densite des defauts crees au cours d'une contrainte sature pour une polarisation drain VDS donnee, au bout d'un temps plus ou moins long suivant la polarisation grille appliquee VGS. Elle met en evidence une relaxation apres une contrainte, d'environ 10 % des defauts crees par les porteurs chauds. Le nombre total de ces defauts n'est pas toujours maximum pour les contraintes VGS = VDS /2 comme il est souvent admis [1].