Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.

Self-Aligned Gate Contact (SAGC) integration is design based on formation of the two separate contacts to the source/drain (S/D) and to the gate (G), which are realized in two separate plasma etch steps. Essentially, the first one is the contact plug (CP) etch over S/D contact selective to the gate plug (GP) and sidewall spacer (SWS), and the second one is the gate plug (GP) etch selective to the contact plug (CP) and the sidewall spacer (SWS). Therefore, the high selectivity plasma etch processing for the CP and GP towards the other two relevant, neighboring films is a key requirement for successful SAGC integration. In this paper we present plasma etch process development required for SAGC implementation, primarily focusing on the multi-color selectivity studies, i.e., selective CP (towards GP and SWS) as well as selective GP (towards CP and SWS) at contacted poly pitch (CPP) 42nm. The primary ('standard') integration scheme uses SiO2 CP, Si3N4 GP and SiCO SWS. Furthermore, we investigate the " alternative' integration scheme with SiCxNy films as replacement of the traditionally used SiO2 CP material aiming to simplify the patterning sequence and ease high selectivity requirements. We report the selectivity values obtained on the CP/GP/SWS multi-color stack for the CP plasma processing (SiO2 or SiCxNy) towards Si3N4 and SiCO; as well as for GP (Si3N4) plasma dry etch process towards SiO2 or SiCxNy and SiCO. Using a Quasi-ALE (Q-ALE) approach for selective SiO2 etch process is developed with a selectivity of 8 to 1 towards Si3N4 and SiCO. For the selective Si3N4 etch continuous wave plasma CH3F-based process is developed and selectivity of 9 to 1 towards SiO2 and SiCO achieved. In the case of the integration scheme with SiCxNy CP, the selectivity for SiCxNy etch towards Si3N4 GP and SiCO SWS higher than 20 to 1 is accomplished using continuous RF source NF3/O-2-based process. As for the Si3N4 plasma etch in the 'alternative' scheme using CH3F/O-2-based process, the selectivity towards SiCxNy of higher than 20 to 1 and selectivity to SiCO of around 10 to1 is achieved.

Multipatterning has enabled continued scaling of chip technology at the 28nm logic node and beyond see Fig. 1. Self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho-Etch/Litho-Etch iterations are widely used in the semiconductor industry to reach sub 193 immersion lithography resolutions for critical layers such as FIN, Gate and Metal lines. Multipatterning requires the use of multiple masks, which is costly and increases process complexity as well as edge placement error variation mostly driven by overlay. In our presentation, we will propose and demonstrate novel patterning concepts, which can curb some of these downsides and usher in the next technological advancements required for further scaling. We will also survey the progress and maturity of EUV patterning in contrast to multipatterning options.

In this paper we present an overview and examples of thin films processing technologies for future generations of leading edge semiconductor devices. We introduce the main driving forces affecting future thin film deposition and etch technologies including the push for 3D (vertical) power, performance and area scaling. We discuss new thin films processes on the near term horizon that enable future devices, improved contacts, scaled 3D interconnects, and advanced patterning technologies followed by a future outlook for scaling.

As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line. In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.

In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5-nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16-nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.

Since its first appearance in 1965, Moore’s law (i.e., the observation that the density of transistors on integrated circuits doubles approximately every two years) has survived many threats to its perpetuity. In fact, it has thrived for the past 20 years.1, 2 With the semiconductor industry on the cusp of the N5 (5nm) technology node, however, this status quo is changing, and— as has been announced by many integrated-device manufacturers and foundries3, 4—areal scaling is approaching a slowdown. One of the key factors to overcoming this slowdown lies in obtaining control over the variability that creeps in during fabrication, leading to yield degradation.5 In patterning, this variability has been quantified as the edge-placement error (EPE). Simply defined, the EPE is the difference between the intended design and the actual on-silicon results. Controlling EPE at N5 and beyond is one of the foremost challenges for semiconductor fabrication. In the development of advanced technology nodes, interconnects in integrated circuits represent a major area for which EPE control is a key factor.5 Critical back-end-of-the-line (BEOL) trench patterning at the N5 node requires a sub-30nm pitch line-space pattern. This small pitch (i.e., center-to-center distance between features) can be achieved using high volume manufacturing (HVM)-ready 193nm immersion-lithography-based self-aligned quadruple patterning (SAQP). However, block patterning (i.e., cutting an as-generated grid into a desired pattern) remains a challenge in terms of EPE. The standard approach for block patterning is shown in Figure 1. For both 193nm immersion-based and 13.5nm extreme UV (EUV)-based block patterning, multiple bright-field pillar-mask-based lithography passes are required (i.e., 4–5 and 2–3 masks, respectively). At the N5 node, this approach is challenging due to two major issues. Figure 1. (a) Traditional block-mask approach for critical back-end-ofthe-line trench patterning on a line grid defined by spacers (i.e., material A). Vertical gray and white lines show the eventual locations of dielectric material and metal wires, respectively (i.e., after metallization). The pink ellipse represents the block mask. Transparent ellipses show examples of bad overlay (with respect to the trench). In such cases, the block mask may cause electrical short circuits. (b) Our multicolormaterial-based approach, in which each color designates a different etch selectivity. In our approach, every other trench is filled with a different sacrificial material (i.e., B and C, which would be a spin-on metal and a type of silicon, respectively). By introducing alternate materials in each trench, overlay variation is made trivial. Based on our calculations, this approach reduces the negative effects of overlay by three times compared to the approach shown in (a).

Critical back end of line (BEOL) trench (M-x) patterning at 7 nm technology node and beyond requires sub-36 nm pitch line/space pattern in order to meet the scaling requirements. This small pitch can be achieved by either extreme ultraviolet (EUV) lithography or 193 nm-immersion-lithography based self-aligned quadruple patterning (SAQP). With enormous challenges being faced in production readiness of EUV lithography, SAQP is expected to be the primary approach for M-x grid patterning. In contrast to the front end of line (FEOL) fin patterning, which has successfully deployed a SAQP approach since the 10 nm node technology, BEOL M-x presents a new challenge owing to the usage of significantly lower temperature budgets for film stack deposition. These temperature budgets have an adverse impact on the film material properties leading to emergence of several challenges for etch including selectivity, uniformity and roughness.In this presentation we will highlight those unique etch challenges associated with our BEOL M-x SAQP patterning strategy and summarize our efforts in optimizing the patterning stack, etch chemistries & process steps for meeting the 7 nm technology node targets. We will present comparison data on both organic and in-organic mandrel stacks with respect to LER/LWR & CDU. With LER being one of the most critical targets for 7 nm BEOL M-x, we will outline our actions for optimization of our stack including resist material, mandrel material, spacer material and others. Finally, we would like to update our progress on achieving the target LER of 1.5 nm for 32 nm pitch BEOL SAQP pattern.

Patterning the desired narrow pitch at 10nm technology node and beyond, necessitates employment of either extreme ultra violet (EUV) lithography or multi-patterning solutions based on 193nm-immersion lithography. With enormous challenges being faced in getting EUV lithography ready for production, multi-patterning solutions that leverage the already installed base of 193nm-immersion-lithography are poised to become the industry norm for 10 and 7nm technology nodes. For patterning sub-40nm pitch line/space features, self-aligned quadruple patterning (SAQP) with resist pattern as the first mandrel shows significant cost as well as design benefit, as compared to EUV lithography or other multi-patterning techniques. One of the most critical steps in this patterning scheme is the resist mandrel definition step which involves trimming / reformation of resist profile via plasma etch for achieving appropriate pitch after the final pattern. Being the first mandrel, the requirements for the Line Edge Roughness (LER) / Line Width Roughness (LWR); critical dimension uniformity (CDU); and profile in 3-dimensions for the resist trim / reformation etch is extremely aggressive. In this paper we highlight the unique challenges associated in developing resist trim / reformation plasma etch process for SAQP integration scheme and summarize our efforts in optimizing the trim etch chemistries, process steps and plasma etch parameters for meeting the mandrel definition targets. Finally, we have shown successful patterning of 30nm pitch patterns via the resist-mandrel SAQP scheme and its implementation for Si-fin formation at 7nm node.

EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve throughput has primarily been through a significant focus on source power which has been a continuing challenge for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for the patterned CD. With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs. If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.

Incorporation of litho-freeze-litho-etch (LFLE) double patterning techniques have had limited uses in the industry due to a number of issues including : LER / LWR degradation of 1st layer patterning during the 2nd exposure, the necessity to utilize thermal `freezing' resists which necessitate the incorporation of alcohol-based resist systems, and the inability of extending such processes to NTD resist platforms which have superior patterning capabilities for specific structures which are attractive for LFLE type of applications. The incorporation of directed current superposition (DCS) `freeze' process enables greater flexibility in the materials selection for a true litho-freeze-litho-etch process without incurring any of the detriments of previous LFLE processes. By creating a method to crosslink and harden the initial resist pattern through interaction of ballistic electrons and through the deposition of a thin SiO2 skin overtop the hardened feature, the initial structure becomes impervious to any solvent attack or exposure-effects associated with typical LFLE processes while simultaneously providing a mechanism to enable a very controllable method for C/H shrink. Additionally, the incorporation of the DCS freeze process provides unlimited flexibility with respect to resist material selection and enables the incorporation of NTD based resists in order to leverage the small trench and hole printing capabilities of these resists in the generation of small contacts and slot contacts through various cross-point double patterning methods. The DCS process can even be tuned to provide LER / LWR benefits to the initial pattern in order to create good fidelity performance of the final structure. We will present results through etch showing the generation of slotted and circular contacts through the LFLE process incorporating the directed current superposition process incorporating multiple type of resist platforms in order to produce a library of different types of contact structures.