The semiconductor industry has witnessed a fast progression of spectroscopic ellipsometry (SE) techniques aimed at resolving a plethora of complex device characterizations on a nanometric scale. The Mueller Matrix (MM) methodology coupled with rigorous coupled-wave analysis (RCWA) has offered an unprecedented power of investigation and analysis of diverse critical dimensions (CDs), especially when applied to gate-all-around (GAA) structures, as it helps increase the useful spectral signals of the often geometrically buried CDs. However, the sensitivity to the CDs can be often screened by other parameters, hampering the precision and accuracy of the measurement. Combining the most sensitive MM elements has therefore become a critical step of scatterometry critical dimension (SCD) metrology. Driven by the rapid developments of Machine Learning (ML) algorithms, we propose a versatile ellipsometry methodology that overcomes poor sensitivity and increases accuracy through a novel principal component analysis (PCA) method of the ML training algorithm with RCWA assistance. Furthermore, our methodology introduces a new ML training concept based on reference data statistics, rather than raw reference. Our approach has been validated with reference data and proved successful in monitoring GAA sheet-specific indent. The proposed methodology paves the way to measuring low sensitivity CDs with highly accurate, noise-reduced and robust ML-based physical SCD models for any logic and memory application.

A spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective analyses of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows for focusing on parameters of interest through dramatically simplified optical modeling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are monitored discussed: (i) the critical dimensions (CDs) of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) the CDs of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy. Furthermore, it was shown that machine learning models trained with VTS filtered data can converge to a robust solution with a smaller dataset compared with models training with traditional scatterometry data.

Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured the focus of the semiconductor industry and have been identified as the lead architecture to continue logic complementary metal-oxide-semiconductor scaling beyond 5 nm node. The fabrication of GAA devices requires specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology progresses through research and development cycles and is poised to transition to manufacturing, there are many opportunities and challenges that still remain for in-line metrology. Especially valuable are measurement techniques that are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact on the frequency of cycles of learning. More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. Thanks to the computing revolution the semiconductor industry enabled, machine learning has begun to permeate in-line disposition, and hybrid metrology systems continue to advance. Of course, metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness, pitch walk, and defectivity continue to be managed. We review related prior studies and advocate for future metrology development that ensures nanosheet technology has the in-line data necessary for success. (c) 2022 Society of Photo-Optical Instrumentation Engineers (SPIE)

—Methodologies for characterization of the lateral indentation of silicon-germanium (SiGe) nanosheets using different non-destructive and in-line compatible metrology techniques are presented and discussed. Gate-all-around nanosheet device structures with a total of three sacrificial SiGe sheets were fabricated and different etch process conditions used to induce indent depth variations. Scatterometry with spectral interferometry and x-ray fluorescence in conjunction with advanced interpretation and machine learning algorithms were used to quantify the SiGe indentation. Solutions for two approaches, average indent (represented by a single parameter) as well as sheet-specific indent, are presented. Both scatterometry with spectral interferometry as well as x-ray fluorescence measurements are suitable techniques to quantify the average indent through a single parameter. Furthermore, machine learning algorithms enable a fast solution path by combining x-ray fluorescence difference data with scatterometry spectra, therefore avoiding the need for a full optical model solution. A similar machine learning model approach can be employed for sheet-specific indent monitoring; however, reference data from cross-section transmission electron microscopy image analyses are required for training. It was found that scatterometry with spectral interferometry spectra and a traditional optical model in combination with advanced algorithms can achieve a very good match to sheet-specific reference data.

Horizontally stacked nanosheet gate-all-around devices enable area scaling of transistor technology, while providing improved electrostatic control over FinFETs for a wide range of channel widths within a single chip for simultaneous low power applications and high-performance computing. Fabrication of inner spacers and Si channels is challenging, but essential to device performance, yield, and reliability. We elucidate these challenges and detail their impact to the device. We overcome these challenges with novel, highly selective, isotropic SiGe dry etch techniques which enable precise, robust inner spacer and channel formation. Finally, we demonstrate substantial improvements to relevant device parameters: resistance, drive current, transconductance, threshold voltage, breakdown voltage, bias temperature instability and overall variability.

In this work, the novel enhancement to multichannel scatterometry data collection, Spectral Interferometry, is introduced and discussed. The Spectral Interferometry technology adds unique spectroscopic data by providing absolute phase information. This enhances metrology performance by improving sensitivity to weak target parameters and reducing parameter correlations. Spectral Interferometry enhanced OCD capabilities were demonstrated for one of the most critical and challenging applications of gate-all-around nanosheet device manufacturing: lateral etching of SiGe nanosheet layers to form inner spacer indentations. The inner spacer protects the channel from the source/drain regions during channel release and defines the gate length of the device. Additionally, a methodology is presented, which enables reliable and reproducible manufacturing of reference samples with engineered sheet-specific indent variations at nominal etch processing. Such samples are ideal candidates for evaluating metrology solutions with minimal destructive reference metrology costs. Two strategies, single parameter and sheet-specific indent monitoring are discussed, and it was found that the addition of spectroscopic information acquired by Spectral Interferometry improved both optical metrology solutions. In addition to improving the match to references for single parameter indent monitoring, excellent sheet-specific indent results can be delivered

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet technology in the FEOL. While sheet and gate pitches expected for the beyond 7nm node fall within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet device performance requirements at technology critical sheet widths and gate lengths. Here, we demonstrate electrical performance of nanosheet FET’s with 20 – 80 nm wide sheets with 40-150 nm pitch gates patterned with single expose EUV. We compare results against a benchmark double patterning process towards meeting variability, device and critical dimension targets. We also explore the limits of process and material knobs - resists, illuminations and etch chemistries with the specific goal of reducing LER/LWR and towards shrink for further scaling. Our results demonstrate crossover points between direct print EUV and double patterning processes for nanosheet technology and identify relevant design guidelines and focus areas to successfully enable EUV for the FEOL in nanosheets.

Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of GAA devices requires new specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology continues through research and development cycles and looks to transition to manufacturing, there are many opportunities and challenges remaining for inline metrology. Especially valuable are measurement techniques which are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact to the frequency of cycles of learning. More than previous nodes, then, this node may be when some of these offline techniques jump from the lab to the fab, as certain critical measurements need to be monitored realtime. Thanks to the compute revolution this very industry enabled, machine learning has begun to permeate inline disposition, and hybrid metrology systems continue to advance. Metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness (LER), pitchwalk, and defectivity continue to be managed. This paper reviews related prior studies and advocates for future metrology development that ensures nanosheet technology has the inline data necessary for success.

As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the threshold voltage (VT) and yield. Metrology challenges for obtaining these metrics arise from increasingly dense arrays coupled with both high aspect ratios, high numbers of correlated parameters, and increasingly complex 3D geometries. Large area metrology structures can be used for 3D parameters' process monitoring through techniques such as scatterometry and x-ray diffraction (XRD) which deliver averaged results over that area, but variation impacting specific devices cannot currently be understood without destructive cross-section. Prior work to characterize the dimensions of these GAA devices has primarily featured optical metrology, X-ray metrology, and critical-dimension scanning electron microscopy (CDSEM), but these techniques have their own challenges at the critical process points. Atomic force microscopy (AFM) had not been utilized due to the aspect ratios and small trench widths which were inaccessible to conventional techniques. However, due to recent advances in scanning and novel probe technologies, AFM is well-suited now to solve these local, three-dimensional challenges. Through this study, we demonstrate AFM characterization of a key process point in the GAA process flow for multiple structures with varying channel lengths, after epitaxial (epi) growth along the Si sidewall. The AFM scan results are compared to CDSEM images for top-down corroboration of topography and to other reference metrology for height correlation. The impact of measured variations in epi height to device performance is also reviewed.

For stacked Nanosheet gate-all-around transistors, a new failure mode between the gate and epitaxial source/drain (PC-Epi) is introduced in the Middle-Of-Line (MOL) intermetal dielectrics (IMD) because of a unique module called inner spacer. In this work, we demonstrate a novel integration scheme for evaluating the inner spacer reliability by completely oxidizing the Si channel. The inner spacer TDDB reliability is also shown to be robust, which is essential to support the continuous aggressive device scaling.

Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet patterning as a replacement to complex double patterning schemes. While front-up sheet pitches and gate pitches expected for the beyond 7nm node fall well within the EUV direct print regime (>40nm), it is unclear if direct print solutions can meet variation requirements at technology minimum sheet widths and gate lengths. Here, we explore the crossover point between direct print EUV and optical/EUV based double patterning processes for sheets and gates in the 40 – 50 nm sheet pitch/CPP regime. We demonstrate that to enable the minimum sheet widths of <20nm required for the technology, direct bright field print with shrink results in high variability. We develop a tone invert process with darkfield sheet print that utilizes a polymerizing etch to reduce variability and achieve sub-20nm sheet widths with reduced variability, comparable to a self-aligned double patterning (SADP) process. With gate length variation requirements being tighter, we show that SADP still yields a considerable improvement in line edge/width roughness over a direct print process. We project EUV technology into the future to quantify improvements that would enable direct printed gates that match SADP. Our results will provide a guideline to down-select patterning processes for the nanosheet front end while optimizing cost and complexity.

The methodology of measuring the lateral etch, or indentation, of SiGe nanosheets by using optical scatterometry, x-ray fluorescence, and machine learning algorithms is presented and discussed. Stacked nanosheet device structures were fabricated with different etch conditions in order to induce variations in the indent. It was found that both scatterometry in conjunction with Spectral Interferometry and novel interpretation algorithms as well as TEM calibrated LE-XRF are suitable techniques to quantify the indent. Machine learning algorithms enabled an additional solution path by combining LE-XRF data with scatterometry spectra therefore avoiding the need for a full optical model.

An analysis of NanoSheet (NS) transistor parasitic resistance components is presented and correlated to the resistance readout on Si wafers. With this model, it is possible to identify which components cause the parasitic resistance increases as CPP (contacted poly-Si pitch) further scales from 48 nm to 44 nm pitch. In this study, an alternative MOL (middle of line) metallization scheme is implemented to reduce circuit RC delay. This model helps to further reduce the transistor parasitic resistance from NFET/PFET S/D (source/drain) epitaxy or silicide. As CPP scales, NS PFET parasitic resistance reduction is more challenging and requires optimization in S/D epitaxy, silicide and metallization. Based on parasitic resistance modeling, we present a new wrap-around contact structure which eliminates the vertical epi resistance component, hence reducing overall device resistance.

We report an improved air spacer (AS) integration scheme to overcome problems with the conventional AS process. The new scheme is fully compatible with other emerging CMOS technology elements such as self-aligned contact (SAC) and contact over active gate (COAG). Using a fan-out3 (FO3) ring oscillator (RO) on a 10-nm FinFET platform, we experimentally demonstrate that the new AS provides 15% reduction in the effective capacitance (C-eff). Such a Ceff reduction translates to 21% performance gain at the constant power (iso-power) or 36% power reduction at the constant performance (iso-speed). The benefits provided by AS exceed the benefits of a full CMOS node scaling from 7 to 5 nm. Clearly, AS is a viable technological element for continuing CMOS scaling.

We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both gate-contact (CB) to source-drain local interconnect (LI) shorts and the LI-contact (CA) to gate shorts is the shape of the LI cap. A trapezoid-shaped oxide (SiO 2 ) LI cap with an appropriate taper angle eliminates shorting between the contacts in the gate and source-drain region. We further demonstrate that this oxide LI cap is fully compatible with Cobalt (Co) metallization with a novel selective tungsten (W) growth process. Additionally, this process enables the SRAM cross-couple (XC) in the same metallization level, eliminating the need for an upper level wiring and greatly simplifying routing in the SRAM cell.

With transistor scaling in 7nm technology and beyond, sacrificial silicon materials etches (e.g. dummy poly silicon gate removal) are considered to be among the most challenging hurdle in FinFET process development. In this paper, we present a dry chemical etch technique for selective etching of single crystal, poly-crystal and amorphous silicon on various FinFET device process steps. It was demonstrated that this technique could completely remove poly silicon in vertically high aspect ratio (AR>5) FinFET gates with a large process window (over-etch budget ~200%) while achieving the lowest gate leakage current and best short channel FET yield. Proper surface preparation, queue time control and etch by-product removal strategies are discussed. The residue free etch and etch by-product sublimation mechanisms are also investigated by High Resolution Electron Microscopy (HREM) and Fourier Transform Infrared Spectroscopy (FTIR) surface analysis. This work was performed by the IBM Research at various IBM Research and Development Facilities.

The characteristics of Stacked Nanosheet are investigated, focusing on channel geometry. For the first time, “narrow sheet effect” on carrier transport is observed. By comparing measured electron $(\mu_{e})$ and hole $(\mu_{h})$ mobilities, and the n-type/p-type opposite transconductance ( $gm$ ) trends versus sheet width ( $Wsheet$ ), we show that the mobility dependency on $Wsheet$ is attributed to reduced (100) plane conduction contribution as $Wsheet$ shrinks.

SiGe FinFET has been explored for its benefit of high current drivability provided by channel strain [1-5]. We have demonstrated SiGe CMOS FinFET at 10nm technology ground rules including epitaxial defectivity control, DC performance and reliability benefit [6-8]. One concern of SiGe FinFET is channel strain relaxation by fin cut process [9] inducing local layout effect (LLE), which is crucial for product design. In this paper, we thoroughly examined LLE in SiGe pFinFET and explored its mitigation techniques. Two techniques are proposed and demonstrated successful LLE mitigation, which drives forward SiGe FinFET insertion to technology.