This work presents the development of single-print metal logic patterning for A14 and A10 technology nodes using the TWINSCAN EXE:5000 at the ASML-imec High-NA lab, following successful pattern transfer via etch. The study focuses on random logic metal designs characterized by tight pitch constraints and aggressive tip-to-tip spacing, addressing the patterning challenges associated with advanced node scaling.

One of the key steps in the pattern formation chain of extreme ultraviolet (EUV) lithography is the development process to resolve the resist pattern after EUV exposure. The traditional development process might be insufficient to achieve the requirements of ultra-high-resolution features with low defect levels. The aim of this paper is to establish a process to achieve a good roughness, a low defectivity at a low EUV dose, and capability for extremely-high-resolution for high numerical aperture (NA) and hyper-NA EUV lithography. A new development method named ESPERT™ (Enhanced Sensitivity develoPER Technology™) has been introduced to improve the performance of metal oxide-resists (MOR). ESPERT™ as a chemical super resolution technique effectively apodized the MOR chemical image, improving chemical gradient (higher exposure latitude (EL)) and reducing scums (fewer bridge defects). This new development method can also keep the resist profile vertical to mitigate the break defects. The performances of the conventional development and ESPERT™ were evaluated and compared using 0.33 NA EUV, 0.5 NA EUV, and electron beam (EB) exposures, for all line-space (LS), contact hole (CH), and pillar (PL) patterns. Using 0.33 NA EUV scanners on LS patterns, both bridge and break defects were confirmed to be reduced for all 32-nm-pitch, 28-nm-pitch, 26-nm-pitch LS patterns while reducing the EUV dose to size (DtS). In the electrical yield (1 meter length) test of breaks/bridges of 26-nm pitch structures, ESPERT™ reduced EUV dose while its combo yield was almost 100% over a wide dose range of 20mJ/cm². For CH patterns, in the case of 32-nm-pitch AEI (after etch inspection), EL was increased 7.5% up to 22.5%, while failure free latitude (FFL) was widened from 1-nm to 4-nm. A 16-nm-pitch LS pattern was successfully printed with 0.5 NA tool, while a 16-nm-pitch PL and an 18-nm-pitch CH patterns were also achieved with an EB lithography by ESPERT™. With ESPERT™, there was no pillar collapse observed for 12-nm half-pitch PL by 0.5 NA and 8-nm half-pitch PL by EB. With all the advantages of having a high exposure sensitivity, a low defectivity, and an extremely-high-resolution capability, this advanced development method is expected be a solution for high-NA EUV towards hyper-NA EUV lithography.

As the semiconductor industry progresses towards the 2nm logic technology node in pursuit of improved chip performance and density, the demand for minimum pitch scaling in the back-end-of-line (BEOL) interconnect becomes crucial. Imec N3 logic design rules defined a minimum Metal 2 (M2) layer pitch of 30 nm, representing 2nm technology nodes. To further enhance semiconductor integrated circuit performance, attention is shifting towards advanced mask materials for current 0.33 NA EUV scanners. Low-n masks have been shown to improve extreme ultraviolet (EUV) imaging performance in terms of Local-CDU (LCDU), reduced mask 3D effects and improved optical contrast compared to a Ta-based mask [1-3]. In our study, we observed notable enhancements in optical contrast for real logic designs using a low-n mask. Our findings demonstrate an impressive LCDU of 5.5 nm and CGDU of 5.5 nm for Place'n'Route (PnR) structures at a pitch of 32. Furthermore, we successfully printed tip-to-tip (T2T) features as small as 20 nm on the wafer for regular tip-to-tip structures that didn't get any Optical proximity Correction (OPC). These advancements mark significant progress towards manufacturability and developing a holistic patterning approach for random logic metal with EUV.

High-NA EUV lithography is currently under development to keep up with device node scaling with smaller feature sizes. In this paper, the most recent advances in EUV patterning using metal oxide resists (MOR) and chemically amplified resists (CAR) are discussed. A newly developed resist development method (ESPERT™) was examined on MOR with 24 nm pitch line and space (L/S) patterns and 32 nm pitch pillars for preparation of high-NA EUV patterning. The patterning results showed improved sensitivity and pattern collapse margin. CAR contact hole patterning at 28 nm pitch was also examined by stochastic lithography simulation. The simulation results indicate that resist film thickness needs to be optimized for target pitches.

Extreme ultraviolet (EUV) lithography has already introduced in high volume manufacturing and continuous improvements has allowed to resolve pitch 24 nm line and space (L/S), pitch 32 nm contact hole and pillar pattern with single exposure at even numerical aperture (NA) 0.33. However, pattern roughness, local critical dimension uniformity (LCDU) and process related defects are still major challenges with decreasing critical dimensions (CD). Pitch downscaling also require the use of thinner photoresist mask to prevent pattern collapse from high aspect ratios. Thinner photoresist mask is challenging for pattern transfer because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. It is required to investigate a co-optimization of lithography processes, underlayers and etch processes to further EUV patterning extension. In this paper our latest developed technology and process solutions to extend the limits of EUV patterning will be report.

In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.

In order to fully utilize the potential of the latest and greatest scanner overlay performance capability in a manufacturing environment, all other (process-induced) overlay contributors should be well understood and eliminated where possible. While overlay penalties that slowly vary across the wafer and/or within each exposure field can easily be corrected with the available scanner correction knobs, this is less likely going to happen for overlay signatures that manifest themselves on a much shorter length scale. We refer to length scales that are comparable to the floorplan of the integrated circuit itself. A deep understanding of these process induced overlay contributions is required to take away their root causes. Several non-scanner overlay contributors are known that may have an impact on the scanner exposure field overlay performance. Of course, the quality of the mask itself plays an important role. Mask writing errors correlate one-to-one with the on-wafer overlay performance. Local stress effects may contribute to the intra-die overlay performance too. We extensively addressed the layer stress impact on the intra-field overlay in an earlier publication. In that work, an interesting observation was made. The etch-induced overlay contribution turned out to be largely independent of the layer stress in which the pattern was etched. The conclusion was drawn that the etch-induced overlay penalties can be optimized separately from layer stress related overlay effects. In this work, the focus will be on the etch-induced overlay penalties only. We addressed the etch-induced overlay impact already before. Surprisingly, the etch-induced overlay penalties showed up in every exposure field despite the fact that the etch tool itself is not exposure field aware. For the use-case we investigated, the magnitude of the etch-induced intra-field overlay penalty was around 1-nm. This comes close to the scanner baseline overlay performance. A relation was found with the pattern density distribution and a dependency with the etch tool settings was observed. We identified the Spin-On-Glass and/or Spin-On-Carbon (Hard Mask) etch as the potential root cause. A hypothesis was proposed that was in line with the experimental observations. In this experimental work, we have continued the investigation by validating the hypothesis proposed earlier. Since the hypothesis was based on the pattern density distribution within the exposure field in combination with the deflection of ions due to surface charging effects, both the mask and the etch tool recipe settings per layer have been changed. We show that the etch-induced intra-field overlay penalties can indeed be controlled by changing the etch tool recipe settings per layer. However, the underlying mechanism turned out to be different from what we expected. In the current paper, we will present a new concept that much better explains all the experimental results we have obtained so far. Based on this new understanding, we experimentally demonstrate that etch-induced intra-field overlay penalties can be mitigated by optimizing the etch tool recipe settings.

EUV (extreme ultraviolet) lithography has been introduced in high volume manufacturing in 2019 and continuous improvements have allowed to push the lithographic performance to the limits of 0.33 NA single exposure. However, stochastic failures, pattern roughness and local critical dimension uniformity (LCDU) are still major challenges that need to be addressed to maintain node shrinkage and improve yield. Together with pitch downscaling, photoresist thickness is decreasing to prevent pattern collapse. A lower depth of focus is also expected with high NA EUV which might even thin further down the resist layer. Being able to transfer the patterns with good fidelity is therefore getting very challenging because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. A co-optimization of lithography processes, underlayers coating and etch processes is essential to further support the EUV patterning extension. In this report, recently developed hardware and process solutions to stretch the limits of EUV patterning will be presented. The latest performance for both chemically amplified resists (CAR) and metal oxide resists (MOR) will be introduced, with a focus on defect mitigation, dose reduction strategies and CD stability.

Extreme ultraviolet (EUV) lithography has been used for mass production for several years. Now the resolution limit of current 0.33 NA single exposure has been approaching. To enhance the resolution limit, high NA exposure tool has been developing. At the limit, not only the stochastic failures1, but also patterning trade-off has been becoming challenging. In this paper, to overcome the patterning trade-off of LS and CH, several approaches were demonstrated for both CAR and MOR. As for chemically amplified resist (CAR), to overcome the patterning trade-off of line and space, two different approaches were demonstrated. One was a developer rinse process optimization, and the other was a top deposition treatment during etching process. By using the two approaches, pitch 24 nm LS patterns were successfully transferred. As to CAR CH patterning, a new shrink technique during etch process was successfully tested for sub 15 nm hole patterning. No missing hole detected at 12 nm hole size by voltage contrast metrology. For tighter nodes, spin-on metal oxide resist (MOR) have been considering to be used because it offers a series of advantages. It has high sensitivity and resolution because of its high photon absorption and simple reaction mechanism. It also inherently has a higher etch resistance which enables resist thickness thinner and collapse margin higher. Spin-on process of MOR is expect to contribute high productivity which is essential for high volume manufacturing (HVM). Because defect reduction is one of the key points to enable MOR process for HVM, continuous investigation of defect mitigation has been done. For pitch 32 nm LS, the mitigation was confirmed by fine optimization with the combination of the etch process and the implementation of new under layers. As to pitch 28nm line and space, optimized illumination gave better defect process windows. Moreover, a new wet developer process was successfully proposed to prevent pitch 36 nm hexagonal pillars collapse during wet development with 25% higher EUV sensitivity.

Inpria has pioneered the development of high-resolution metal oxide (MOx) photoresists designed to unlock the full potential of EUV lithography. In addition to resolution, LWR, and sensitivity to enable advanced process nodes, there are also stringent defectivity requirements that must be realized for any resist system. We will review advances in post-etch defectivity based on: resist design and formulation, track process design, developer design, and etch optimization. We will present data supporting each of these topics quantifying the defect impact and will describe improvement strategies to take full advantage of such MOx resist systems.

Extreme ultraviolet (EUV) lithography faces major challenges for smaller nodes due to the impact of stochastic and processing failures.1 One of the main challenges for pitch shrink at these nodes is the optimization of the trade-off between break type defects versus bridge type defects as the process window between these defect modes gets smaller.2 In this paper, we examine EUV defect reduction techniques for Chemically Amplified Resist (CAR) and Metal Oxide Resist (MOR) via coater/developer process development combined with optimized etching processes.

EUV (extreme ultraviolet) lithography is progressively being inserted in high volume manufacturing of semiconductors to keep up with node shrinkage. However, defectivity remains one big challenge to address in order to be able to exploit its full potential. As in any type of lithographic process, processing failures and in-film particles are contributors that need to be reduced by the optimization of coating and development processes and improved dispense systems. On top of these defects, stochastic failures, due to photon shot noise or non-uniformities in the resist, are another major contribution to the defectivity. To support their mitigation, etch process can be used to avoid their transfer to underlying layers. However, it requires a sufficient resist mask thickness. For line and space patterns, providing more resist budget comes with a trade-off which is the increase of pattern collapse failures, especially with shrinking critical dimensions. Collapse mitigation approaches are therefore very important to enable tight pitches and were explored. Stack engineering and especially optimization of resist under layers will be crucial components to enable patterning and defect reduction of shrinking pitches. Finally, as an alternative to traditional chemically amplified resists, metal containing resists are also promising because of their inherent high etch resistance. Dedicated hardware and processes were developed the use of such materials and prevent metal contamination to other tools during further processing steps. In this report will be presented the latest solutions to further decrease defectivity towards manufacturable levels and provide more process margin to achieve better quality patterning towards the limits of NA 0.33 EUV exposure. Furthermore, technologies to improve CD uniformity and stability, which are required for mass production, will also be reported.

Extreme ultraviolet (EUV) lithography has been begun high volume manufacturing (HVM). To allow for robust processing, both CAR and novel metal oxide resist (MOR) materials are needed, but they each come with unique challenges specific to the layer being printed. CAR resist shows good capability for CH printing and pattern transfer. However, specific processing techniques for the pattern transfer is required to mitigate LCDU issues. Additionally CAR L/S printing shows robust capability at 18nm HP, but when approaching 16nm HP, the defect process window is impacted by collapse and bridging. For ultimate resolution, novel materials such as MOR have been demonstrated but sensitivities of the materials for CD stability and defectivity need to be mitigated. TOKYO ELECTRON investigates ways to reduce these risks with a novel approach for coating process, post exposure bake, and developing sequence. This paper reports technologies to improve CDU, PW, and defectivity. In addition, we report solutions of solving metal contamination risk for MOR while maintaining productivity.

Recently, the etch induced on-product overlay contribution as part of the total on-product overlay budget has received more attention. The main reason for this is that the etch induced overlay penalties are comparable to or even exceeding the state-of-the-art scanner overlay performance of approximately 1-nm. Large values from 4-nm to as much as 15-nm have been reported at the edge of the wafer. In order to mitigate these overlay penalties, solutions have been developed by both scanner and etch tool companies. Since the scanner has the capability to apply corrections per exposed field, the corrections can be optimized such that the overlay performance after etch is within the required specification. A potential drawback of this solution is that the underlying root cause is not taken away. A tilt in the etch direction that is causing the etch induced overlay penalty is compensated by a lateral offset by the scanner. A more elegant and preferred solution would be to optimize the etch tool hardware and/or etch recipe settings such that the etch direction is perpendicular to the wafer surface at every location on the wafer. To this end, dedicated hardware has been developed inside the etch chamber to compensate for the etch tilt in the etch direction at the wafer edge. Etch induced overlay effects were more recently also observed within each individual exposure field. A clear correlation with the pattern density distribution was found. Since these overlay penalties are static and repetitive from field to field, etch tool hardware changes are likely not the way forward to eliminate these kinds of overlay errors. For non-uniform pattern density distributions, a deep understanding of the details of the etch mechanism in combination with an optimized etch recipe is currently being considered to eliminate the intra-field etch induced overlay contributions. In earlier publications, the main focus was either on characterizing the etch impact on overlay or on understanding the impact of stressed layers on overlay. In this paper, we address the overlay impact after etching thin films that are deposited with either compressive or tensile stress. The deposition of the stressed films results in so-called umbrella- or bowl-shaped wafers. By varying the film thickness and composition, four different splits have been defined with warp levels of 40-μm and 80-μm for both shapes, respectively. First, the etch contribution for the different stressed layers is quantified. We will show that the etch induced overlay contribution does not depend on whether the stress in the deposited layer is compressive or tensile. This means that the etch induced overlay can be optimized independently of the properties of the stressed layer. Since the mask used has a non-uniform pattern density distribution, the stress distribution within the exposure field after the etching process will be non-uniform as well. This has a direct impact on the measured overlay after resist development for the subsequent litho layers. We will provide more clarity on the origin and nature of this overlay contributor. The goal of this paper is to characterize and better understand the overlay contributors associated with stressed layer etch. Additionally, we will provide solution directions to mitigate these overlay penalties.

The etch induced on-product overlay performance across wafer has received quite some attention recently. Global wafer overlay penalties have been observed by realizing that the etch direction is not always perpendicular to the wafer surface and may vary slightly as a function of the wafer radius due to the geometry and plasma parameter settings of the etch tool. In particular close to the wafer edge, for radii in between 130-mm and 150-mm, the etch direction may change even more strongly and is not constant over time. This is due to a consumable part inside the etch tool, the so-called focus ring. Control solutions based on optical overlay metrology have been developed and have found their way into tunable focus rings. The general concept is to keep the etch direction perpendicular to the wafer surface throughout the life-time of the focus ring. The general belief is that these global etch induced overlay penalties can be mitigated by applying these newly developed hardware control solutions. In this experimental work, we go one level deeper and consider the more local etch induced overlay penalties. This time etch effects on length scales on the order of exposure field and/or die level are addressed. The intra-field etch induced overlay penalties are characterized by considering the overlay measurement after resist development (ADI) and after etch (AEI). Surprisingly, the observed penalties are on the order of ~1-nm within each individual exposure field despite the fact that away from the wafer edge the etch direction is considered to be close to perpendicular to the wafer surface. In this experimental work, etch tool parameters like low frequency (LF) power and pressure have been varied to reveal the nature of these die-level overlay penalties. Based on the experimental results, we present a hypothesis of the underlying mechanism that explains the etch induced intra-field overlay penalties and provide solution directions to mitigate these kinds of overlay penalties.

In this work, we present and compare two integration approaches to enable self-alignment of the block suitable for the 5-nm technology node. The first approach is exploring the insertion of a spin-on metal-based material to memorize the first block and act as an etch stop layer in the overall integration. The second approach is evaluating the self-aligned block technology employing widely used organic materials and well-known processes. The concept and the motivation are discussed considering the effects on design and mask count as well as the impact on process complexity and EPE budget. We show the integration schemes and discuss the requirements to enable self-alignment. We present the details of materials and processes selection to allow optimal selective etches and we demonstrate the proof of concept using a 16-nm half-pitch BEOL vehicle. Finally, a study on technology insertion and cost estimation is presented.

EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.