In this paper, we have investigated the flicker noise (1/ $f$ ) in 45-nm RFSOI NFETs for quantum computing applications. 1/ $f$ noise characterization and analysis were performed in linear region at cryogenic temperatures down to 10K. A Lorentzian-like noise is also observed depending on bias conditions, possibly due to the floating body of PDSOI. The extracted frequency exponent $(\gamma)$ shows an inverted U-shape behavior with temperature mainly attributed to non-uniform energy distribution of traps in the gate dielectric. The dominant source of 1/ $f$ noise is carrier number fluctuation. Thermal-activation behavior of 1/ $f$ noise is studied, which shows the traps responsible for noise are not thermally activated. Volume trap densities are also extracted from 300K down to 10K. The volume trap density increases with a decrease in temperature, but no significant increase in normalized noise is observed at cryogenic temperatures in the measured NFETs. The non-uniform distribution along with the thermal inactive behavior of traps over the studied temperature range is expected to be a plausible reason for the temperature-independent behavior of normalized noise.

DC curves and S-parameters up to 30 GHz measured before and after hot-carrier-injection (HCI) stress in non-conducting (NC) mode are used to study the degradation suffered by the small-signal input and output impedances of a PD-SOI MOSFET. Modeling of the gate oxide $\boldsymbol{(R_{ox})}$ and channel resistance $(\boldsymbol{R_{ch}})$ due to NC-HCI is also performed and investigated in detail. Noticeable impact on the device's input resistance is seen for the first time up to frequencies of 500 MHz, but it is expected to increase further into the microwave frequency range as the gate leakage increases due to either device degradation or large applied gate voltage.

The aim of this paper is to analyze the time-dependent dielectric breakdown (TDDB) in MOSFETs at cryo temperatures deployed in control circuitry for quantum computing applications. The effect of cryogenic temperatures down to 10K on TDDB in 45-nm RFSOI n-channel MOSFETs is studied here. From Weibull distribution, it is seen that the characteristic breakdown time (t63) increases with decreasing temperature with a weak saturation effect at ultra-low temperatures. Weibull slope $(\beta)$ shows an inverted U-shaped trend exhibiting a maximum between 100-200K at all measured voltages. Very low activation energy (Ea) is seen at cryo temperatures and Ea decreases with temperature lowering in three distinct temperature regions. The voltage acceleration exponent (VAE) increases with decrease in temperature down to $\sim 77\text{K}$ followed by a decrease with decreasing temperature. The trap generation rate and critical defect density are estimated and the trend of $\beta $ is explained within the framework of the multiple origins of breakdown in the measurement window. Significant sample size for each condition with variability was taken into account for all parameters to improve the confidence level in our results.

This work aims to study the temperature dependence on the long-term reliability of a power amplifier (PA) cell fabricated using 40-nm partially depleted-silicon on insulator (PD-SOI) nFET under dc and large-signal RF stress. Voltage swing caused by large RF signals complicates the stress mechanism due to frequent switching of stress from conducting to nonconducting. The impact of temperature on the time slope exponent ( ${n}$ ) is also analyzed to understand the degradation mechanism at different temperatures. The values of ${n}$ are found to increase with the temperature pointing to the generation of new defects at the interface. A comparative reliability analysis is presented for dc, small-, and large-signal performance under varied accelerated dc and large-signal stress at drain and gate for different temperatures. Unity gain frequencies are also temperature sensitive and show high degradation at elevated temperatures. In our study, we have investigated the lifetime as a function of temperature of the PA operating in compression. It is observed that the lifetime is more than ten years when the PA operates at room temperature, which deteriorates as the measurement chuck temperature rises.

RF long term aging and large signal reliability in 22FDX Wi-Fi Power Amplifier (P A) designs is investigated. Packaged PA operating at 5.4GHz., 3.3V V DD with LDMOS as Common Gate and SLVT as Common Source is stressed under accelerated DC and RF power conditions for +1.5kPOH at TA=25 C. A custom built Power Amplifier Test System (PATS) tool capable of large signal on packaged samples is used for long term stress. Initial RF performance of ~26 dBm., with gain 14~15 is seen before stress. Power sweeps at regular stress intervals were performed to validate PA degradation. Self-heating effect is studied by correlating T A to junction temp T J using thermal models. Thermal images confirm that higher P diss leads to higher T J . Output power degradation of < 0.5dB is seen at accelerated voltage of 4.2V after + 1.5kPOH which is correlated to voltage swings. Key limiting mechanism for common gate and source devices are identified, demonstrating the viability of CMOS FDSOI technology for 5G applications.

For the first time, the temperature dependence of RF reliability of a power amplifier (PA) is investigated for the mmWave frequency band. The PA comprises a common source configured single pFET fabricated in 45RFSOI technology by GlobalFoundries. Temperature dependence of DC and large-signal figures of merit (FOMs) are analysed as a function of RF power levels and DC stress at the gate terminal for a continuous wave (CW) frequency of 26.5GHz. In this study, we have also investigated the relationship between temperature and the time slope exponent obtained from the % degradation in ON current $(I_{ON})$ for different operating regions of PA. The degradation mechanism involves trapping hot holes in pre-existing traps and the generation of new traps in the oxide due to hot holes. A non-linear relationship between DC and RF FOMs $(I_{ON}$ and $P_{OUT})$ is investigated for the increasing temperature. The non-linear relationship extracted from the slope between ${\Delta }I_{ON}$ and ${\Delta }P_{OUT}$ shows that the DC performance is impacted more than the RF performance with the increasing temperature. Degradation in output power of PA cell increases with the temperature. As a result, the lifetime of PA cell decreases with increasing temperature and fails to achieve a 10-year lifetime.

This Special Issue is devoted to research and development in the field of electron devices science and technology. We have selected a number of high-quality papers presented at the 4th Latin American Electron Device Conference (LAEDC 2022). The forth LAEDC edition took place in Puebla, Mexico, from July 4th to 6th, 2022 and was sponsored by the IEEE Electron Devices Society.

In this work, we have investigated the reliability degradation mechanisms in RF switches for 45nm RFSOI technology under DC and RF stress modes. We have used single-pole single-throw RF switches using thin and thick gate oxide in series stacked configurations using $\boldsymbol{R_{ON}. C_{OFF}}$ as a key metric. Degradation and breakdown depend on stress time, DC gate and drain voltages, and RF power. The mechanism causing degradation is studied using the voltage swings at the terminals of the RF switch. In addition, stress recovery is also observed in some cases, which is critical for switches used in transceivers. Overall, the switch exhibits superior reliability under RF 5G mmWave operating conditions.

RF reliability of 40-nm PDSOI nFET power amplifier (PA) cell at 26.5GHz is investigated. DC and RF stresses are applied in conducting and non-conducting hot carrier stress modes to study the PA cell RF and DC degradation behavior. The relationship between DC and large-signal RF performance under various RF stress conditions is investigated using DC and RF metrics. The degradation rate depends on RF power and terminal voltages, where ~8X lower degradation is observed at low VGS. During RF stress, the DC performance degradation rate is higher in the linear operating region than the saturation region. The impact of RF stress is amplified in the presence of DC stress, accelerating the degradation of PA cells. For different VGS under RF stress conditions, the lifetime of the PA cell is calculated and compared.

This paper presents an extensive experimental analysis of hot carrier degradation (HCD) due to DC and large-signal RF stress on a power amplifier (PA) cell in the sub-7GHz frequency band. The reported PA cell is fabricated in a 45-nm RFSOI technology and consists of a single n-channel floating body partially depleted SOI FET. The impact of HCD on the class, conduction angle ( $\theta $ ), and performance of the PA cell is analyzed under DC and large-signal RF stress conditions. Generation of defects and their types, i.e., whether oxide or interface traps, are understood using a combination of RF and DC stress conditions. Our detailed analysis distinguishes HCD mechanisms dominated by oxide and interface traps by studying time slope exponents, changes in the subthreshold swing, threshold voltage, and peak transconductance. The impact of RF stress on the PA cell lifetime is also extracted using a semiempirical model.

RF High Temperature Operating Life (HTOL) of a 5G mmWave beamformer chip is evaluated at 28GHz under worst case operating life conditions. Each packaged chip with 8 channel Power Amplifier used for generating omnidirectional beam was evaluated for >= 120hrs at 0.1%CCDF under accelerated Psat RF stress at Tj ~ 85C. Excellent initial RF metrics were observed for all ~24 samples measured. Overall Pout and gain degrade by <0.5dB while DC current degrades <10% meeting the 10yr product life criteria demonstrating excellent RF HTOL processed using GF 45RFSOI technology. Excellent aging model to hardware correlation was also observed confirming the validity of the models at mmWave frequencies.

The sub-THz spectrum between 100GHz and 300GHz is of great interest for achieving next generation 6G cellular network goals of ultra-high data rate, ultra-low latency and high sensing precision. Carrier frequencies >100GHz create significant challenges, including higher losses, lower semiconductor device performance, and a smaller per element physical area that constrains circuit size, integration, power and thermal management. Semiconductor technologies with transistor performance >500GHz are needed for improved efficiency, gain, noise and area at the front end of the 6G phased array radio. Advances in SiGe BiCMOS have the potential to increase silicon transistor performance while leveraging the cost and scale of mature high-volume silicon manufacturing for 6G sub-THz. Compound semiconductor technologies such as InP and GaN have the best front end performance at sub-THz. Advances in heterogeneous and monolithic integration with silicon are needed to address the cost and scale concerns of high frequency InP and GaN. A comprehensive approach to reliability is essential in order to extract maximum performance without sacrificing reliability.

We have investigated and report here for the first time time-dependent dielectric breakdown (TDDB) in 45-nm RFSOI n-channel floating body MOSFETs at cryogenic temperatures. DC constant voltage stress is applied at the gate while the substrate chuck temperature is varied from 300K down to 10K. While t63 decreases with increasing temperature, shape parameter β shows an inverted U-shaped behavior which is explained using the bandgap model. Three levels of activation energy are seen for high, low and deep low temperatures where the activation energy decreases from high to deep low temperatures. The observed behavior is further explained using carrier energy shift in the bandgap as per the percolation theory.

This Special Issue is devoted to research and development in the field of electron devices science and technology. We have selected a number of high-quality papers presented at the 3rd Latin American Electron Device Conference (LAEDC 2021). The third LAEDC edition took place virtually, from April 19th to 21st, 2021 and was sponsored by the IEEE Electron Devices Society.

Two key mechanisms (i) trapping induced Parasitic Drain Series Resistance (PDSRI) and (ii) interface state generation ΔNit are both identified within non-conducting hot carrier injection (NCHCI). During NCHCI stress, the drain current degradation due to PDSRI is observed at the first time readout as a sudden shift and is followed by conventional (relatively lower) monotonically increasing shift due to interface state generation. The convolution of these two phenomena, complicates the extraction of their unique model parameters and lifetime extrapolation. Characterization methods to isolate each is demonstrated. Their separate dependencies on gate length, drain voltage, and temperature are studied and modeled. Using TCAD simulations, the differences in the damage rate and location due to PDSRI and ΔNit are studied. By understanding the E-field distribution, the charge trapping in the side wall spacer region is found to be the key contributor to PDSRI behavior under NCHCI conditions.

This paper reports the flicker noise (1/f) analysis of NFETs fabricated using a 45-nm partially depleted silicon on insulator (PDSOI) RFCMOS technology. The noise characterization and analysis are performed at different chuck temperatures down to −20 °C in linear region of operation. It has been found that the normalized drain current noise power spectral density increases with increasing temperature up to 120 °C. The carrier number fluctuation model has been used to successfully explain the measured 1/f noise at these temperatures. The trap densities extracted at gate overdrive voltage of 0.1 V and 0.15 V are found to increase with increasing temperature, as only electrically active traps within a few kT of the surface Fermi level (E F ) contribute to 1/f noise. In addition, the frequency exponent γ is < 1 for all temperatures, which indicates non-uniform distribution of traps across the energy bandgap.

In this letter, we have explored the DC, small and large-signal RF reliability of the Power Amplifier (PA) cell for mm-wave applications under DC and RF stress. The PA cell comprises of a single transistor that employs 45RFSOI technology. For the first time here, a PA cell consisting of p-channel partially depleted Silicon-On-Insulator (PD-SOI) FET has been investigated for large-signal reliability behavior. At the same stress conditions, the impact of hot carrier degradation (HCD) on a p-channel FET (PFET) PA cell is also compared with the n-channel FET (NFET) PA cell. As the reliability of the PFET PA cell is superior than NFETs, a deeper investigation of hot carrier degradation and its impact on PA cell reliability is carried out. The PA cell is subjected to extensive RF characterization for varying DC stress and RF power at the gate terminal. The behavior of the time slope exponent of the PFET PA cell is studied to understand the nature of defects. Accelerated aging experiments using DC bias at drain/gate terminals and RF power at the gate terminal is performed. These results show that the RF reliability of the PFET PA cell is superior than its counterpart NFET PA cell at mm-wave frequencies.