We propose a sub-μW always-ON keyword spotting (μKWS) chip for audio wake-up systems. It is mainly composed of a neural network (NN) and a feature extraction (FE) circuit. For significantly reducing the memory footprint and computational load, four techniques are used to achieve ultralow-power consumption: 1) a serial-FFT-based Mel-frequency cepstrum coefficient circuit is designed for FE, instead of the common parallel FFT. 2) A small-sized binarized depthwise separable convolutional NN (DSCNN) is designed as the classifier. 3) A framewise incremental computation technique is devised in contrast to the conventional whole-word processing. 4) Reduced computation allows a low system clock frequency, which enables near-threshold voltage operation, and low leakage memory blocks are designed to minimize the leakage power. Implemented in 28-nm CMOS technology, this μKWS consumes 0.51 μW at a 40-kHz frequency and a 0.41-V supply, with an area of 0.23 mm2. Using the Google speech command data set, 97.3% accuracy is reached for a one-word KWS task and 94.6% for a two-word task.

As a widely used speech-triggered interface, deep-learning based keyword spotting (KWS) chips require both ultra-low power and high detection accuracy. We propose an always-on keyword spotting chip with an acoustic activity detection (AAD) to achieve the above two requirements. Extracted from feature extractor, this AAD has zero overhead and zero miss rate. It is used to clock gate the neural network and post processing unit to achieve ultra-low power at silent scenarios. We also propose a tunable detection window to fit keywords with different widths to get better accuracy. Besides, a non-overlapping-frame Mel frequency cepstrum coefficient (MFCC) is used in the KWS system to reduce memory footprint and processing cycles. Implemented in a 28nm CMOS technology, its power consumption is only $0.36\mu\mathrm{W}$ for AAD at quiet scenarios and $0.8\mu\mathrm{W}$ for KWS, operating at 0.4V supply voltage with 8kHz for MFCC and 200kHz for other parts. And MFCC circuit has only 170nW power consumption. The accuracy can reach 97.8% for two keywords in the Google speech command data set (GSCD).

Excessive timing margins are usually added in the wide-voltage-range design due to process, voltage and temperature (PVT) variations, which can be eliminated by adaptive voltage scaling (AVS). Some traditional Razor-based designs replace endpoint flip-flops with latches and ensure data sampled correctly. The duration of time-borrowing and the short path problem make the minimum-delay constraint worthy of consideration. To overcome the minimum-delay problem in the latch-based error detection and correction (EDAC) techniques, we propose a solution using a pulsed-latch and transition detector (TD). This method utilizes time-borrowing characteristics of the latch to ensure the correct function. To detect timing violations and minimize area overhead, we design a 15-transistor transition detector which is able to operate at a wide voltage range, from near-threshold voltage (NTV) to super-threshold voltage (STV). To minimize the overhead of pulse generators, a physical allocation-aware pulse generator insertion algorithm is presented to identify each desired group of a pulse generator and a pulsed-latch group. The proposed scheme is implemented in an 8-bit AES circuit through an automatic insertion flow and fabricated in a 28nm CMOS process. Chip measurements demonstrate that the whole design achieves up to 64.3% energy saving as compared to the conventional worst-case design at a small price of 4.3% area overhead.

Ultra-low power is a strong requirement for always-on speech interfaces in wearable and mobile devices, such as Voice Activity Detection (VAD) and Keyword Spotting (KWS) [1]-[5]. A KWS system is used to detect specific wake-up words by speakers and has to be always on. Previous ASICs for KWS lack energy-efficient implementations having power . For example, deep neural network (DNN)-based KWS [1] has a large on-chip weight memory of 270KB and consumes 288μW. A binarized convolutional neural network (CNN) used 52KB of SRAM, 141μW wakeup power at 2.5MHz, 0.57V [2]. An LSTM-based SoC used 105KB of SRAM and reduced power to 16.11μW for KWS with 90.8% accuracy on the Google Speech Command Dataset (GSCD) [3]. Laika reduced power to 5μW [4], not including the Mel Frequency Cepstrum Coefficient (MFCC) circuit. High compute and memory requirements have prevented always-on KWS chips from operating in the sub-μW range.

An energy-efficient AES hardware accelerator based on 2-Sbox 8-bit datapath is fabricated in 28nm CMOS for IoT and mobile SoC applications. It obtains the smallest encryption cycles of 113 of 8b-AES by 100% utilization of two Sboxes and rearranging data bytes processing order. It also minimizes intermediate data registers (InterReg) to only 40b from 256b by eliminating ShiftRow and MixColumn registers. Along with glitch reduction design of Sbox in native GF(2 4 )2 composite-field, it achieves best-in-class efficiency of 257923 Gbps/W and 28-991Mbps throughput rate at 0.41/0.9V with scalable voltage down to near-threshold.

Hardware countermeasure of side channel attack (SCA) becomes necessary to protect crypto circuits. Many countermeasures endured large area and power consumption. We propose a SCA-resistant methodology based on machine learning, which compensates the Hamming distance (HD) probability of the intermediate data directly. By making the HD probabilities unable to be distinguished from correct and incorrect sub-keys, it provides resistance to SCA. Optimum HD redistribution is obtained by a machine learning algorithm and then sent to the compensation circuit. Applied in an Advanced Encryption Standard (AES)-128 circuit, the whole compensated circuit is implemented on a 28-nm CMOS process. The experimental results show that it resists correlation-based SCA with 1.5 million traces, corresponding to 446 $\times $ improvements of measures to disclosure compared with a nonprotected AES circuit. In addition, it has no impact on the frequency and throughput rate, and its power overhead of 38% and area overhead of 36% are relatively low, making it suitable for resource-constrained encryption circuits.

As an emerging paradigm for energy-efficiency design, approximate computing can reduce power consumption through simplification of logic circuits. Although calculation errors are caused by approximate computing, their impacts on the final results can be negligible in some error resilient applications, such as Convolutional Neural Networks (CNNs). Therefore, approximate computing has been applied to CNNs to reduce the high demand for computing resources and energy. Compared with the traditional method such as reducing data precision, this paper investigates the effect of approximate computing on the accuracy and power consumption of CNNs. To optimize the approximate computing technology applied to CNNs, we propose a method for quantifying the error resilience of each neuron by theoretical analysis and observe that error resilience varies widely across different neurons. On the basic of quantitative error resilience, dynamic adaptation of approximate bit-width and the corresponding configurable adder are proposed to fully exploit the error resilience of CNNs. Experimental results show that the proposed method further improves the performance of power consumption while maintaining high accuracy. By adopting the optimal approximate bit-width for each layer found by our proposed algorithm, dynamic adaptation of approximate bit-width reduces power consumption by more than 30% and causes less than 1% loss of the accuracy for LeNet-5.

In recent years, many applications of voice wake-up technology have entered people's lives and the key technology is Keyword Spotting (KWS). The keyword spotting system needs to detect the ambient voice and wait for a wake-up at any time, which requires low power consumption and high recognition accuracy. We mainly aim at reducing the power consumption of real-time keyword spotting systems in this paper. Based on Google's speech commands dataset (GSCD), a deep neural network model with Depthwise Separable Convolution (DS-Conv) is constructed and trained. We propose a kind of Approximate Multiply and Accumulate Unit (AP-MAC) and a data reuse method called Streaming Convolution Reuse (SCR) and prove that the neural network with AP-MACs saves 37.7% ~ 42.6% of computing power and achieves similar Word Error Rate (WER) compared to the same model using traditional MAC units in KWS task. Also, SCR allows the model to reuse convolution results for multiple audio frames and saves 94% of activations storage. By combining these two methods, the computing power and memory storage per audio frame of the baseline model are reduced by 98.5% ~ 98.7% and 94% respectively.

The security issue of Internet of Things (IoT) applications causes wide concern nowadays. Lightweight encryption circuits are preferred in IoT due to its severe restrictions of chip area and power consumption, among which, 8-bit datapath Advanced Encryption Standard (AES) is popular for its mature algorithm, compact architecture and low power consumption. However, it is also subject to the side channel analysis (SCA) attack, which is rarely mentioned. In this paper, a novel differential power analysis (DPA) attack method specialized for 8-bit datapath AES is proposed, which exploits the correlation between the power consumption of S-Box and processed data. The method can traverse all the possibilities. As a result, it is effective for almost all the existing 8-bit AES architecture in theory. The first round of encryption is adopted as the target round, avoiding the complicated computing in AES algorithm to reduce the cost of attack and increase the success rate and efficiency. The effectivity of this kind of method is verified by FPGA implementation on SAKURA-G board, with a minimum of 3681 power traces to crack the correct sub-key.

Lightweight AES encryption circuits are significant to IoT applications to protect data, where very strict area and power constraints are required. In this paper, we propose a novel 8-bit datapath AES architecture aiming for a small area and a high energy efficiency. Firstly, our proposed design reduces the number of temporary data storage (IntermediateReg) to 40-bit from the originally 128-bit, which saves 68.75% intermediate registers. Secondly, only one S-Box is implemented in the design that is reused throughout the whole AES operations to achieve a low area. Thirdly, the architecture is further optimized to reduce the number of clock cycles by reusing S-Box in the key expansion and the data encryption module, leading to only 213 total cycles of latency in a complete encryption process. Simulation results under TSMC 28nm technology show that our proposed AES circuit consumes an area of 0.0028mm 2 , with an energy efficiency of 667Gbps/W (equivalent to 1.50 pJ/bit) and throughput rate of 30.05Mbps at 0.5V. This design achieves a high energy efficiency per unit area of 0.278 Gbps/(W·um 2 ). This small area, high energy efficiency and relatively high throughput AES circuit is suitable for IoT applications.

To overcome the minimum-delay constraint of latch based error detection and correction (EDAC) techniques, we propose a technique of using pulse latch and transition detector (TD). This method is also advantageous in no need of error recovery by time-borrowing characteristics of the latch. To detect timing violations and minimize the area overhead, we design a quick-response 15-transistor transition detector cover a wide-voltage range from near-threshold voltage (NTV) to Super-Vth. Test chips are fabricated in 28nm CMOS process. Silicon measurements demonstrate that the whole design has achieved up to 64.3% energy saving with 180mV additional voltage scaling, compared to the conventional worst-case design at the expense of 4.3% area overhead.