Formal verification techniques ensure completeness as opposed to simulation-based techniques. In general, the process of formal verification is computationally complex, and it is difficult to quantify the exact time and space complexities. Some of the recent works have shown that it is possible to achieve polynomial space and time complexities for verifying specific designs, like arithmetic circuits. However, this cannot be directly extended to complex circuits, like processors. A recent work has reported a formal verification method for the RISC-V processor with polynomial complexity, where only single-cycle instruction execution was considered and it was computation intensive. This method cannot be directly extended to multi-cycle operations, which are typical for most real processors. This paper introduces an improved data structure leading to Binary Decision Diagram (BDD) based Polynomial Formal Verification (PFV) with support for both single-cycle and multi-cycle operations. We use the MicroRV32 processor as a case study. Our method leads to significant improvement in runtime over the previous method. The entire process of verification can be carried out in polynomial space and time complexities for multi-cycle operations.
Controlling of resistive switching properties by optical means opens the route to new optoelectronics that can be written optically and read electronically. In this work, we demonstrate optically controlled memristors realized with a hybrid material of vertically aligned zinc oxide nanorods (ZnO NRs) and poly(methyl methacrylate) (PMMA). In addition to electronic switching, the devices are switchable by optical means upon illumination with UV light. The hybrid memristors require no forming step and exhibit multilevel switching behavior achieved by controlling either the DC sweep voltage or the UV light power. The optical memristor exhibits irreversible switching for the Off state, which has an important application in the fabrication of cloned neural networks with pre-trained information. The work provides a promising pathway for the fabrication of simple-to-make and low-cost optoelectronic devices for memory and optically tuned neuromorphic computing applications.
Convolutional neural networks (CNNs) are widely used in computer vision, natural language processing, and other application scenarios. But deploying CNNs at the edge is challenging due to their large number of parameters. Pruning is a solution that can effectively reduce the number of parameters and off-chip memory accesses. However, high sparsity unstructured pruning is not hardware-friendly, while structured pruning has low compression efficiency. As a result, vector-level pruning, with a coarser granularity, is a promising alternative that balances pruning performance and hardware-friendliness. In this paper, a hardware-oriented vector-level pruning strategy is proposed based on the CNN vector distribution properties. By expanding the dynamic range of vector groups, more important weights can be preserved without sacrificing accuracy. When applied to the VGG-16 and ResNet-18 models on the ImageNet dataset, the proposed strategy achieved 10.93 × and 10.17 × compression ratios in convolutional layers with a 66% reduction in computation and an acceptable drop in top-1 accuracy. Furthermore, the proposed pruning scheme achieves a remarkable performance of 188 FPS on the VCU118 evaluation board, demonstrating its compatibility with hardware. Compared to the state-of-the-art, the proposed strategy reaches 69% performance improvement and up to 2.8 × higher LUT efficiency.
Hyper Dimensional Computing is a new approach in artificial intelligence (AI). The specific requirements of massive parallel readout operation during HDC inference makes the high-impedance ferroelectric tunneling junction (FTJ) devices a very interesting candidate for the hardware realization of a HDC accelerator. Therefore, we propose to research both, the technological and the architectural constraints when bringing together this two distinct concepts from the architectural and the devices perspective.
Multi-valued logic (MVL), characterized by more than two possible logic states, presents distinct advantages compared to conventional Boolean logic. Novel post-CMOS technologies, particularly memristive and bio-sensitive devices, exhibit compelling attributes that make them promising candidates for realizing MVL computing components. To assess the viability of these devices, we delve into key aspects of Memristive and ISFETs, including their state transition dynamics, multi-level functionality, and compatibility with CMOS manufacturing processes. Through this investigation, we successfully demonstrate the practical implementation of ternary arithmetic MVL gates utilizing memristive and bio-sensitive devices. Our findings affirm that these innovative devices hold the potential to serve as MVL computing elements effectively.
The Cellular Nonlinear Network (CNN) is a powerful paradigm in analog computing. As pure-CMOS based CNN Universal Machine faces the von Neumann bottleneck, the integration of memristive devices with their non-volatile memory properties is of major interest. These networks are called Memristor-CNNs (M-CNNs). Moreover, the integration of memristors brings richer dynamics into the network, such that M-CNNs are highly suitable for neuromorphic computing tasks. This paper presents the experimental verification of a processing unit of an uncoupled M-CNN design with a valance change mechanism (VCM) based memristor. We outline a simple measurement strategy to study M-CNNs with real-world devices and provide compelling evidence that the results of the M-CNN processing element are stored in a non-volatile manner. This work further offers crucial insights into design considerations of M-CNN networks.
Many consumer products such as wearable and disposable electronics require flexibility, biocompatibility and ultra low-costs, which can hardly be matched by silicon electronics. Therefore, printed electronics (PE) becomes a competitive candidate thanks to its additive manufacturing. To address fundamental signal-processing tasks, printed neuromorphic circuits (pNCs) have received increasing attention, as they can achieve promising computational capabilities by assembling simple circuit primitives. However, many target domains of PE are based on processing temporal sensory data, which can not be reached by existing pNCs, since they lack components with time dependencies. This paper proposes a printed temporal processing block that combines existing pNCs with learnable filters. We model the proposed circuit and proposed the corresponding training objective to enable their bespoke design. Simulations on 15 benchmark time-series datasets reveal that, the proposed circuits can effectively process temporal data by using 1.5 × and 1.3 × of device counts and power respectively. The classification accuracy reaches 98% of that from classic Elman recurrent neural networks.
Noise is one of the most challenging aspects of cellular nonlinear networks adversely affecting their functionality. Existing techniques to addressing the issues posed by noise are based on well-understood noise removal methods that have reached technical maturity and further have the disadvantage of limited success rates. A deeper understanding and modeling of noise dynamics and its origins are required for the efficient identification and resolution of problems in different network applications. The Stochastic template concept in this article can be beneficial in understanding and modeling noise dynamics in cellular nonlinear networks, which is critical for addressing challenges in network applications. In this paper, memristors functioning as synapses introduce noise into networks, and we conduct an initial investigation of a noisy network performing edge detection.
Valence change mechanism (VCM)-based memristive devices are interesting candidates for computing in memory and neuromorphic applications. For these devices read noise is a characteristic which is influenced by a variety of factors like the switching mode, namely the area-dependent and the filamentary mode. In this paper we use TiOx-based devices as an example system exhibiting both modes. This allows to only investigate the effect of the modes while excluding other influences. We find that the read noise in the area-dependent mode is lower than for the filamentary mode and that abrupt current jumps are primarily seen for the filamentary mode. This has to be taken into account when choosing the right operation mode for a specific application.
The Internet makes use of high performance network switches in order to route network traffic from end users to servers. Despite line-rate performance, the current switches consume huge energy and cannot support more expressive learning models, like cognitive functions using neuromorphic computations. The major reason is the use of transistors in the underlying Ternary Content-Addressable Memory (TCAM) which is volatile and supports digital computations only. These shortcomings can be bypassed by developing network memories building on novel components, like Memristors, due to their nonvolatile, nanoscale and analog storage/processing characteristics. In this paper, we propose the use of a novel memristor-based Probabilistic Associative Memory, PAmM, which provides both digital (deterministic) and analog (probabilistic) outputs for supporting cognitive computational models in network switches. The traditional digital operations can be supported by a memristor-based energy efficient TCAM, called TCAmMCogniGron. Building on PAmM and TCAmMCogniGron, we propose a novel network switching architecture and analyze its energy efficiency over the experimental dataset of a Nb-doped SrTiO3 memristive device. The results show that the proposed network switching architecture consumes only 0.01 fJ/bit/cell energy for analog compute operations which is at least 50 times less than the digital operations.
Reinforcement learning (RL) has shown its viability to learn when an agent interacts continually with the environment to optimize a policy. This work presents a memristor-based deep reinforcement learning (Mem-DRL) system for on-chip training, where the learning process takes place in a dynamic cartpole environment. Memristor device variability is taken into account to make the study more realistic. The proposed system utilized an analog ReLU module to reduce analog to digital converter usage. The analog Mem-DRL system consumed 191 times less energy than an optimized digital FP16 computing system. Our Mem-DRL system reduced the ADC usages by 40%, which led to reduced the overall system energy by 42%. Mem-DRL is 2.4 times faster than the FP16 system and performs 9.27 GOPS during DRL training. The system exhibited an energy efficiency of 23.8 TOPS/W.
research-article Open Access Share on Electrical Properties of Proteinoids for Unconventional Computing Architectures Authors: Panagiotis Mougkogiannis Computer Science and Creative Technologies, University of the West of England, United Kingdom Computer Science and Creative Technologies, University of the West of England, United Kingdom 0000-0003-1710-4917Search about this author , Andrew Adamatzky School of Computing and Creative Technologies, University of the West of England, United Kingdom School of Computing and Creative Technologies, University of the West of England, United Kingdom 0000-0003-1073-2662Search about this author Authors Info & Claims NANOARCH '23: Proceedings of the 18th ACM International Symposium on Nanoscale ArchitecturesDecember 2023Article No.: 26Pages 1–4https://doi.org/10.1145/3611315.3633264Published:25 January 2024Publication History 0citation0DownloadsMetricsTotal Citations0Total Downloads0Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteView all FormatsPDF
The computing-in-memory (CIM) technology effectively addresses the bottleneck of data movement in traditional von-Neumann architecture, especially for deep neural network (DNN) acceleration. However, with the improving performance and parallelism of CIM processing elements (PEs), the substantial latency and power overhead caused by high-density intermediate results transmission has become a new bottleneck in CIM architectures. In this paper, we propose a spatial-designed CIM architecture based on the emerging Monolithic 3D (M3D) technology, and a spatiality-aware DNN mapping method for high-performance CIM systems. The proposed architecture introduces a novel hierarchy by implementing staggered tiers, enabling PEs to be shared by multiple tiles, and uses the ultra-dense and lower-power Inter-Layer Vias (ILVs) as shared buses, enabling CIM PEs to exploit the ultra-high bandwidth of M3D for inter-tile and intra-tile data transfer. Experiment result shows that the proposed M3D-enabled CIM architecture, combined with the proposed mapping method, achieves a 6.52× latency improvement, a 40.84× interconnection energy-delay product (EDP) improvement, and a 7.62× system-level EDP improvement compared to state-of-the-art CIM architecture.
Silicon Dangling Bonds (SiDBs) constitute a beyond-CMOS computational nanotechnology platform that enables higher integration density and lower power consumption than contemporary CMOS nodes. Recent manufacturing breakthroughs in the domain sparked the interest of academia and industry alike in the race for a green computation future at the nanoscale. However, as the fabrication of SiDBs requires atomic precision, SiDB logic systems are inherently susceptible to environmental defects and material variations, which inevitably occur. The Operational Domain is a methodology to evaluate the resilience of SiDB logic against physical parameter variations. However, state-of-the-art implementations require a quadratic number of exponentially complex physical simulator calls to assess the operational domain. This paper presents two novel algorithms to obtain operational domains in an efficient fashion: one based on flood fill, and one based on contour tracing. Experimental evaluations confirm that they reduce the number of required simulator calls by 70.87% and 95.29 %, respectively. Particularly contour tracing achieves the shift from a quadratic to a linear relation, thereby reducing the complexity and paving the way for realizing reliable SiDB-based computing systems.
Memristor crossbar-based neural networks perform parallel operation in the analog domain. Ex-situ training approach needs to program the predetermined resistance values in the memristor crossbar. Because of the stochasticity of the memristor devices, programming a memristor needs to read the device resistance value iteratively. Reading a single memristor in a crossbar (without isolation transistor) is challenging due to the sneak path current. Programming a memristor in a crossbar to either RON or ROFF state is relatively straightforward. A neural network implemented using higher precision weights provides higher classification accuracy compared to a Ternary Neural Network (TNN). This paper demonstrates the implementation of memristor-based neural networks using only the two resistance values (RON, ROFF). At the same time, it achieves higher weight precision. The experimental result shows that the proposed higher precision synapses are easy to program and provide better classification accuracy compared to a TNN.
This paper presents low power circuit design using dynamic gate diffusion input (GDI) technology in Carbon nanotube field effect transistor (CNTFET) technology. GDI technique offers low power with fewer transistor counts and less complexity of circuit and CNTFET technology offers low short channel effect (SCE). NAND and XOR gates-based full adder and two-bit multiplier is designed using the GDI technique and performance analysis is done for various parameters namely power consumption, delay, and power delay product (PDP). Results show that NAND gate-based circuits perform better than XOR-based circuits. Also dynamic GDI NAND gate-based circuits accounts for less power with more flexibility as compared to conventional CMOS-based NAND gate circuits.
In stochastic computing (SC), data is represented using random bit-streams. The efficiency and accuracy of SC systems rely heavily on the stochastic number generator (SNG), which converts data from binary to stochastic bit-streams. While previous research has shown the benefits of using low-discrepancy (LD) sequences like Sobol and Halton in the SNG, the potential of other well-known random sequences remains unexplored. This study investigates new random sequences for potential use in SC. We find that Van Der Corput (VDC) sequences hold promise as a random number generator for accurate and energy-efficient SC, exhibiting intriguing correlation properties. Our evaluation of VDC-based bit-streams includes basic SC operations (multiplication and addition) and image processing tasks like image scaling. Our experimental results demonstrate high accuracy, reduced hardware cost, and lower energy consumption compared to state-of-the-art methods.
- We report on the electrical effects of single and double polymer (polymethacrylate) barriers on polyethylene oxide (PEO) based memristors. The single barrier device with an active layer embedded with WS2 quantum dots is also investigated. The addition of a single PMA barrier yields multi cross point current-voltage hysteresis while the addition of embedded quantum dots removes multi-cross point behavior and shows repeatable uni-polar switching with the device starting in the low resistive state (LRS). The device shows some capability of reversible unipolar to bipolar operation as a function of applied voltage and device rest time. The addition of a double PMA barrier produces a reproducible unipolar switching behavior and a unipolar negative differential resistance behavior at higher voltage operation.
The Von-Neumann bottleneck is one of the biggest problem to achieve higher computing performances and energy efficiency, especially in data centric applications. One of these application, the Internet of Things (IoT), is expanding at an impressive pace and is relying massively on sensors with limited energy to work. The emergence of new CMOS compatible technologies like ferroelectric field effect transistor (FeFET) allows to design new kind of Logic-in-Memory (LiM) operators. These non-volatile operators are expected to help overcoming the Von-Neumann Bottleneck as it will retain information thanks to the non volatility of the FeFET. The amount of data transfer will decrease thanks to this particularity. However, design of new computing operators is a long process. It is important to know if these operators are interesting to pursue into further development, which is why they need to be evaluated. To this extent, we present in this article a Non-volatile Operators Emulation Platform. the platform is based on the COMET RISC-V processor and use emulation to evaluate the impact of new non-volatile memories based operator on the processor performances in terms of number of instruction.
Modeling bias – the difference between the test accuracy obtained by a reference network prototype and a simulated model of that prototype – is explored in the context of hafnia-based ferroelectric field effect transistor (FeFET) devices. Device operating conditions are investigated as a parameter for mitigating the impact of device-to-device variability on the underlying network performance. The computational framework includes a physics-based compact model with artificial variance to sample device data and a multivariate Kriging model to create jump table device models; this framework is a fast and efficient technique to model device populations for realistic neural network simulations. Neural network simulations elucidate optimal operating conditions for practical implementation of FeFET neuromorphic circuits. Future work will include experimental verification and performance comparison against other neuromorphic emerging-memory technologies such as resistive random-access memory (ReRAM) in terms of neural network performance.
