Neural network processors and accelerators are domain-specific architectures deployed to solve the high computational requirements of deep learning algorithms. This article proposes a new instruction set extension for tensor computing, TCX, using Reduced Instruction Set Computer (RISC) instructions enhanced with variable length tensor extensions. It features a multi-dimensional register file, dimension registers, and fully generic tensor instructions. It can be seamlessly integrated into existing RISC Instruction Set Architectures and provides software compatibility for scalable hardware implementations. We present a tensor accelerator implementation of the tensor extensions using an out-of-order RISC microarchitecture. The tensor accelerator is scalable in computation units from several hundred to tens of thousands. An optimized register renaming mechanism is described that allows for many physical tensor registers without requiring architectural support for large tensor register names. We describe new tensor load and store instructions that reduce bandwidth requirements using tensor dimension registers. Implementations may balance data bandwidth and computation utilization for different types of tensor computations such as element-wise, depthwise, and matrix-multiplication. We characterize the computation precision of tensor operations to balance area, generality, and accuracy loss for several well-known neural networks. The TCX processor runs at 1 GHz and sustains 8.2 Tera operations per second using a 4,096 multiply-accumulate compute unit. It consumes 12.8 mm 2 while dissipating 0.46W/TOPs in TSMC 28-nm technology.

Neural network processors and accelerators are domain-specific architectures deployed to solve the high computational requirements of deep learning algorithms. This paper proposes a new instruction set extension for tensor computing, TCX, with RISC-style instructions and variable length tensor extensions. It features a multidimensional register file, dimension registers, and fully generic tensor instructions. It can be seamlessly integrated into existing RISC ISAs and provides software compatibility for scalable hardware implementations. We present an implementation of the TCX tensor computing accelerator using an out-of-order microarchitecture implementation. The tensor accelerator is scalable in computation units from several hundred to tens of thousands. An optimized register renaming mechanism is described which allows for many physical tensor registers without requiring architectural support for large tensor register names. We describe new tensor load and store instructions that reduce bandwidth requirements based on tensor dimensions. Implementations may balance data bandwidth and computation utilization for different types of tensor computations such as element-wise, depth-wise, and matrix-multiplication. We characterize the computation precision of tensor operations to balance area, generality, and accuracy loss for several well-known neural networks. The TCX processor runs at 1 GHz and sustains 8.2 Tera operations per second using a 4096 multiplication-accumulation compute unit with up to 98.83% MAC utilization. It consumes 12.8 square millimeters while dissipating 0.46 Watts per TOP in TSMC 28nm technology.

Unmanned aerial systems capable of beyond visual line of sight operation can be organized into a top-down hierarchy of layers including flight supervision, command and control, simulation of systems, operating systems, and physical hardware. Flight supervision includes unmanned air traffic management, flight planning, authorization, and remote identification. Command and control ensure drones can be piloted safely. Simulation of systems concerns how drones may react to different environments and how changing conditions and information provide input to a piloting system. Electronic hardware controlling drone operation is typically accessed using an operating system. Each layer in the hierarchy has an ecosystem of open-source solutions. In this brief survey we describe representative open-source examples for each level of the hierarchy.

High bandwidth requirements are an obstacle for accelerating the training and inference of deep neural networks. Most previous research focuses on reducing the size of kernel maps for inference. We analyze parameter sparsity of six popular convolutional neural networks - AlexNet, MobileNet, ResNet-50, SqueezeNet, TinyNet, and VGG16. Of the networks considered, those using ReLU (AlexNet, SqueezeNet, VGG16) contain a high percentage of 0-valued parameters and can be statically pruned. Networks with Non-ReLU activation functions in some cases may not contain any 0-valued parameters (ResNet-50, TinyNet). We also investigate runtime feature map usage and find that input feature maps comprise the majority of bandwidth requirements when depth-wise convolution and point-wise convolutions used. We introduce dynamic runtime pruning of feature maps and show that 10% of dynamic feature map execution can be removed without loss of accuracy. We then extend dynamic pruning to allow for values within an epsilon of zero and show a further 5% reduction of feature map loading with a 1% loss of accuracy in top-1.

Deep neural networks have been applied in many applications exhibiting extraordinary abilities in the field of computer vision. However, complex network architectures challenge efficient real-time deployment and require significant computation resources and energy costs. These challenges can be overcome through optimizations such as network compression. Network compression can often be realized with little loss of accuracy. In some cases accuracy may even improve. This paper provides a survey on two types of network compression: pruning and quantization. Pruning can be categorized as static if it is performed offline or dynamic if it is performed at run-time. We compare pruning techniques and describe criteria used to remove redundant computations. We discuss trade-offs in element-wise, channel-wise, shape-wise, filter-wise, layer-wise and even network-wise pruning. Quantization reduces computations by reducing the precision of the datatype. Weights, biases, and activations may be quantized typically to 8-bit integers although lower bit width implementations are also discussed including binary neural networks. Both pruning and quantization can be used independently or combined. We compare current techniques, analyze their strengths and weaknesses, present compressed network accuracy results on a number of frameworks, and provide practical guidance for compressing networks.

We describe a programmable and scalable Convolutional Neural Network (CNN) hardware accelerator optimized for mobile and edge inference computing. The accelerator is comprised of 4 heterogeneous engines - input engine, filter engine, post processing engine, and output engine. The specialized engines execute independently and concurrently. All engines have a core set of common instructions with each engine further specialized for specific functions. We describe the operation of each engine and provide silicon validated results for a number of CNN networks including LeNet-5, TinySSD, and SqueezeNet. We describe a blind modulation detection application using SqueezeNet. The accelerator has been fabricated in 28nm CMOS and runs at 1GHz. The logic consumes 0.6 mm 2 and the fully hardened core with 2MB of SRAM including built-in self-test consumes 9.36mm 2 . The accelerator's filter engine implements 288 f16 multipliers thereby achieving 288 GFLOPS at 1GHz. Two TOPS of peak performance is achieved with all engines running in parallel. The accelerator including SRAM dissipates 193mW running LeNet-5 at room temperature.

We propose a novel approach for semantic segmentation that uses an encoder in the reverse direction to decode. Many semantic segmentation networks adopt a feedforward encoder-decoder architecture. Typically, an input is first downsampled by the encoder to extract high-level semantic features and continues to be fed forward through the decoder module to recover low-level spatial clues. Our method works in an alternative direction that lets information flow backward from the last layer of the encoder towards the first. The encoder performs encoding in the forward pass and the same network performs decoding in the backward pass. Therefore, the encoder itself is also the decoder. Compared to conventional encoder-decoder architectures, ours doesn't require additional layers for decoding and further reuses the encoder weights thereby reducing the total number of parameters required for processing. We show by using only the 13 convolutional layers from VGG-16 plus one tiny classification layer, our model significantly outperforms other frequently cited models that are also adapted from VGG-16. On the Cityscapes semantic segmentation benchmark, our model uses 50.0% less parameters than SegNet and achieves an 18.1% higher "IoU class" score; it uses 28.3% less parameters than DeepLab LargeFOV and the achieved "IoU class" score is 3.9% higher; it uses 89.1% fewer parameters than FCN-8s and the achieved "IoU class" score is 3.1% higher. Our code will be publicly available on Github later.

High bandwidth requirements are an obstacle for accelerating the training and inference of deep neural networks. Most previous research focuses on reducing the size of kernel maps for inference. We analyze parameter sparsity of six popular convolutional neural networks AlexNet, MobileNet, ResNet-50, SqueezeNet, TinyNet, and VGG16. Of the networks considered, those using ReLU (AlexNet, SqueezeNet, VGG16) contain a high percentage of 0-valued parameters and can be statically pruned. Networks with Non-ReLU activation functions in some cases may not contain any 0-valued parameters (ResNet-50, TinyNet). We also investigate runtime feature map usage and find that input feature maps comprise the majority of bandwidth requirements when depth-wise convolution and point-wise convolutions used. We introduce dynamic runtime pruning of feature maps and show that 10% of dynamic feature map execution can be removed without loss of accuracy. We then extend dynamic pruning to allow for values within an epsilon of zero and show a further 5% reduction of feature map loading with a 1% loss of accuracy in top-1.

Shared virtual memory simplifies heterogeneous platform programming by enabling sharing of memory address pointers between heterogeneous devices in the platform. The most advanced implementations present a coherent view of memory to the programmer over the whole virtual address space of the process. From the point of view of data accesses, this System SVM (SSVM) enables the same programming paradigm in heterogeneous platforms as found in homogeneous platforms. C++ revision 17 adds its first features for explicit parallelism through its “Parallel Standard Template Library” (PSTL). This paper discusses the technical issues in offloading PSTL on heterogeneous platforms supporting SSVM and presents a working GCC-based proof-of-concept implementation. Initial benchmarking of the implementation on an AMD Carrizo platform shows speedups from 1.28X to 12.78X in comparison to host-only sequential STL execution.

The paper presents a Software Defined Radio (SDR) development platform with wideband tunable RF (Radio Frequency) front end. The platform is based on the SB3500 Multicore Multithreaded Vector Processor and it is intended to be used for a wide variety of communication protocols as: Time Division Duplexing/Frequency Division Duplexing Long Term Evolution (TDD/FDD LTE), Global Positioning System (GPS), Global System for Mobile/General Packet Radio Service (GSM/GPRS), Wireless Local Area Network (WLAN), Legacy Worldwide Interoperability for Microwave Access (WiMAX). As an example, we describe briefly the implementation of the LTE TDD/FDD communication protocol. As far as we know, this is the only LTE category 1 communication protocol entirely developed and executed in software (SW), without any hardware (HW) accelerators.

In this paper, we describe the Heterogeneous System Architecture Foundation's application to digital signal processors (DSP) and hardware accelerators. We provide an overview of the HSA runtime, system architecture and programmer's model, identify characteristics of DSPs and compare differences in algorithms to GPUs. We show an example mapping of HSA agents to a modern DSP using the HSA intermediate language.

This special issue contains extended articles of the selected papers from the research and development (R&D) track of the wireless innovation Forum's SDR'13-WinnComm conference on wireless communications technologies and software defined radio.Established in 1996, the Wireless Innovation Forum TM is an non-profit ''mutual benefit corporation'' dedicated to advocating for the innovative use of spectrum, and advancing radio technologies that support essential or critical communications worldwide.Forum members bring a broad base of experience in software defined radio (SDR), cognitive radio (CR) and dynamic spectrum access (DSA) technologies in diverse markets and at all levels of the wireless value chain to address emerging wireless communications requirements through enhanced value, reduced total life cost of ownership, and accelerated deployment of standardized families of products, technologies, and services.The Forum acts as the premier venue for its members to collaborate to achieve these objectives, providing opportunities to network with customers, partners and competitors, educate decision makers, develop and expand markets and advance relevant technologies.The Technical Conference was first established in 2002 after a highly successful workshop held in 2001.Now attracting a broad range of delegates from over 20 different countries, the conference is the only event devoted to the advancement of reconfigurable radio technologies from research through deployment.A unique feature of this conference is in providing opportunities to network from a broad mix of participants from all levels of the wireless value chain including investors, commercial network operators, radio manufacturers, system integrators, government procurement officials, regulators, technology providers, engineering service providers, and consultants.The academically focused papers are submitted to the R&D track of the conference.This year's paper topics included software defined radio implementations and architectures, communications signal processing, physical layer techniques, chip implementations, GPUs, FPGAs, processors, RF technologies, security, software systems, software communication architecture, spectrum sharing, cognitive radio, system implementation, and testing.This special issue specifically highlights the selected R&D papers from the 2013 SDR'13-WinnComm conference.The extended papers were evaluated by world experts in software defined radio, cognitive radio, dynamic spectrum access, and communications system design.This special issue contains 18 articles.A network simulation model framework for SDR is discussed by Sapello, Serban, Sethi, Chiang, and Moeltner.The framework takes into account time delays in the SDR processes and supports reconfiguration.The accuracy and scalability are evaluated in the paper.A hardware-accelerated design space exploration framework for communication systems is proposed by Kock, Hasselbarth, Pfitzner, and Blume.The framework combines high-level tools with system-on-chip template

In this paper, we present an implementation of a long term evolution (LTE) system on a software defined radio (SDR) platform using a conventional personal computer that adopts a graphic processing unit (GPU) and a universal software radio peripheral2 (USRP2) with a URSP hardware driver (UHD) to implement an SDR software modem and a radio frequency transceiver, respectively. The central processing unit executes C++ control code that can access the USRP2 via the UHD. We have adopted the Ettus Research UHD due to its high degree of flexibility in the design of the transceiver chain. By taking advantage of this benefit, a simple cognitive radio engine has been implemented using libraries provided by the UHD. We have implemented the software modem on a GPU that is suitable for parallel computing due to its powerful arithmetic and logic units. A parallel programming method is proposed that exploits the single instruction multiple data architecture of the GPU. We focus on the implementation of the Turbo decoder due to its high computational requirements and difficulty in parallelizing the algorithm. The implemented system is analyzed primarily in terms of computation time using the compute unified device architecture profiler. From our experimental tests using the implemented system, we have measured the total processing time for a single frame of both transmit and receive LTE data. We find that it takes 5.00 and 8.58 ms for transmit and receive, respectively. This confirms that the implemented system is capable of real-time processing of all the baseband signal processing algorithms required for LTE systems.

Emerging wireless applications consistently demand higher data rates. Unfortunately, it is challenging to achieve high data rates within the limited amount of available frequency spectrum. Hence, enhanced spectral efficiency and link reliability within the available frequency spectrum are of the utmost importance in current and next generation wireless protocols. To attain high spectral efficiency and link reliability, wireless protocols employ increasingly complex 2-dimensional techniques that involve computationally-intensive matrix operations. Multiple-Input Multiple-Output (MIMO) communication is an example of a promising technique employed by wireless protocols to deliver higher data rates at the cost of increased algorithmic complexity. Application Specific Integrated Circuits (ASICs) have traditionally been used to implement compute-intensive wireless protocols. The wireless industry has been gradually moving towards an alternative programmable platform called Software Defined Radio (SDR) due to its significant benefits, such as reduced development costs, and accelerated time-to-market. The computationally-intensive matrix operations used in current and next generation wireless protocols are extremely expensive to implement in SDR platforms with conventional Digital Signal Processor (DSP) instruction sets. Hence there is a need for novel instructions, hardware designs and algorithm enhancements to enable higher spectral efficiency on SDR platforms. In this paper, we propose Single Instruction Multiple Data (SIMD) CoOrdinate Rotation DIgital Computer (CORDIC) instruction set extensions with CORDIC hardware support to speedup computationally-intensive matrix decomposition algorithms. The CORDIC instruction set extensions have been implemented on the Sandbridge Sandblaster SB3000 SDR platform and evaluated on conventional algorithms used for decomposing a closed loop 4-by-4 Worldwide Interoperability for Microwave Access (WiMAX) MIMO channel into independent Single-Input Single-Output (SISO) channels. Our experimental results on the closed-loop MIMO channel decomposition using CORDIC instructions demonstrate more than 6x speedup over a Sandblaster baseline implementation that uses state-of-the-art SIMD DSP instructions. The CORDIC instructions also provide similar numerical accuracy when compared to the baseline implementation. The techniques we propose in this paper are also applicable to other SDR and embedded processor architectures.

Since H. Yao proposed the lattice reduction (LR)-aided detection algorithm for the MIMO detector, one can exploit the diversity gain provided by the LR method to achieve performance comparable to the maximum likelihood (ML) algorithm but with complexity close to the simple linear detection algorithms such as zero forcing (ZF), minimum mean squared error, and successive interference cancellation, etc. In this paper, in order to reduce the processing time of the LR-aided detector, a graphics processing unit (GPU) has been proposed as the main modem processor in such a way that the detections can be performed in parallel using multiple threads in the GPU. A 2X2 multiple input multiple output (MIMO) WiMAX system has been implemented using a GPU to verify that various MIMO detection algorithms such as ZF, ML, and LR-aided methods can be processed in real-time. From the experimental results, we show that GPUs can realize a 2X2 WiMAX MIMO system adopting an LR-aided detector in real-time. We achieve a processing time of 2.75 ms which meets the downlink duration specification of 3 ms. BER performance of experimental tests also indicates that the LR-aided MIMO detector can fully exploit diversity gain as well as ML detector.

This paper presents an implementation of a 2 × 2 Multi-Input Multi-Output Software Defined Radio (SDR) Base Station system using a Message Passing Interface (MPI)-based Graphic Processing Unit (GPU) cluster as its modem processor for a high-speed data processing. Recently, GPUs have been widely researched especially for SDR systems because of their capability for exploiting parallel processing using a large number of Arithmetic Logic Units. MPI-based GPU clusters have been adopted in order to further increase performance capability. From our experimental results, it has been found that the implemented system consisting of three GPU nodes can enhance the modem speed by more than 2.5 times compared to a single GPU system. A dual-mode Mobile Device (MD) prototype supporting Worldwide Interoperability for Microwave Access and Long Term Evolution communications systems is implemented. In our design, one of the two waveforms can automatically be selected by the MD itself using a dual-mode controller that determines the reconfiguration of the MD modem depending on the received signal quality.

This special issue contains extended articles based on the best papers of the R&D track of the Wireless Innovation Forum's SDR'11-WinnCommConference on Wireless Communications Technologies and Software Defined Radio (SDR).The Wireless Innovation Forum (previously known as the SDR Forum) was established in 1996.The Wireless Innovation Forum TM is a non-profit ''mutual benefit corporation'' dedicated to driving technology innovation in commercial, civil, and defense communications around the world.Forum members bring a broad base of experience in SDR, Cognitive Radio(CR), and Dynamic Spectrum Access (DSA) technologies in diverse markets and at all levels of the wireless value chain to address emerging wireless communications requirements through enhanced value, reduced total life cost of ownership, and accelerated deployment of standardized families of products, technologies, and services.The Forum acts as the premier venue for its members to collaborate to achieve these objectives, providing opportunities to network with customers, partners and competitors, educate decision makers, develop and expand markets, and advance relevant technologies.The Technical Conference was first established in 1992 after a highly successful workshop held in 1991.Now attracting a broad range of about 500 delegates including researchers, professors, industry developers, investors, commercial network operators, radio manufacturers, system integrators, government procurement officials, regulators, engineering service providers, and consultants from over 22 different countries, the conference is the only event devoted to the advancement of reconfigurable radio technologies from research through deployment.We are pleased to report that the annual US conference and product exhibition continues to hold its place in the advanced wireless community as the premier event for exploring SDR, CR, and DSA technologies.Last year there was continued strong participation in this conference.In spite of the continuing down turn in the economy in many segments of the market, our papers were downloaded more than 81,000 times.A unique feature of this conference is in providing opportunities to network from a broad mix of participants from all levels of the wireless value chain including investors, commercial network operators, radio manufacturers, system integrators, government procurement officials, regulators, technology providers, engineering service providers, and consultants.Of this group 42 % were researchers and technology developers.From this group of researchers, academically focussed papers are submitted to the Research and Development (R&D) Track of the conference.This year's paper topics included SDR implementations and architectures, Com-