A demonstration of vertically stacked heterogeneous chiplets featuring Duplexer and LNA/SOI is showcased in this work demonstrating the possibilities in miniaturizing RF front-end modules. By placing the duplexer on LNA/SOI, a simple 3D stacked package with Through-Silicon Via (TSV) in the LNA/SOI enables vertical connectivity between the chiplets. This paper provides an in-depth exploration of the design considerations for chiplet stacking, RDL layout, and TSV placement on LNA/SOI to ensure optimized RF performance of the stacked duplexer and LNA/SOI. Additionally, it covers key aspects of wafer fabrication processes, C2W bonding assembly, and mechanical analysis on wafer warpage. The paper also presents the results of frequency domain functional testing for the stacked duplexer on LNA/SOI, as well as package reliability testing outcomes under MSL3, TC500, and TCoB 500.

The development of ultrafine-pitch microbumps and the thermal compression bonding (TCB) process for advanced 3-D stacking technology are discussed in this paper. Microbumps, consisting of Cu pillars and thin Sn caps with a pitch of 25 μm, are fabricated on an Si chip by the electroplating method. Total thickness of the Cu pillar and the Sn cap is 10 μm. Electroless nickel and immersion gold pads with a total thickness of 4 μm are fabricated on an Si carrier. TCB of the Si chip and the Si carrier is conducted on an FC150 flip-chip bonder, and a good joining with higher than 10-MPa die shear strength is achieved. After bonding, the bond line thickness between the Si chip and the Si carrier is filled with the selected capillary underfill material. Void-free underfilling is achieved with underfill materials which have a fine filler size. Ninety percent of the bonded samples can pass the thermal cycling test (-40/+125°C) with 1000 cycles and the highly accelerated temperature/humidity stress test (130°C , 85% RH) for 96 h.

Fabrication of high aspect ratio through silicon vias (TSVs) in a Si interposer and fine pitch solder microbumps on a top Si die is discussed in this paper. Chip stacking result of the Si interposer and the top Si die is also presented. TSVs with 25 μm in pitch and aspect ratio higher than 10 are etched with BOSCH process. To avoid difficulties in wetting the sidewall of the TSVs, bottom-up plating method is used to fill the TSVs with Cu. In order to fill the TSVs from bottom, the TSVs are first sealed from the bottom by plated Cu with plating current of 1 A. The plated Cu is used as a seed layer and bottom-up plating is then conducted with plating current of 0.1 A. Good filling without voids or with only tiny voids has been achieved. Electroless nickel/immersion gold is plated on top of the TSVs as under bump metallurgy pads. On the top Si die, Cu pillars/Sn caps with 16 μm in diameter and 25 μm in pitch are fabricated with electroplating method. After chip stacking, interconnections are formed between them through the solder microbumps and the TSVs.

This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 x 10mm(2) micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100 mu m bump pitch and 1,124 I/O; the other micro-bumped chip had 50 mu m bump pitch and 13,413 I/O. The TSV interposer size is 25 x 25 x 0.3mm(3) with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 x 45mm(2) with 1-2-1 layer configuration, a ball-grid array (BGA) of 1 mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment.The objective of this paper was to incorporate two 8 x 10mm(2) micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.

Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies are discussed in this paper. The solder microbumps developed in this work consist of Cu and Sn, which are electroplated in sequential with total thickness of 10µm; The under bump metallurgy (UBM) pads used here is electroless plated nickel and immersion gold (ENIG) with thickness of 2µm. Accordingly, joining of the two Si chips can be conducted by joining CuSn solder microbumps to ENIG UBM pads or CuSn solder microbumps to CuSn solder microbumps. The first joining can only be done with chip to chip assembly whereas the second joining has the potential for chip to wafer assembly. Assembly of the Si chips is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

High density three dimensional (3D) interconnects formed by high aspect ratio through silicon vias (TSVs) and fine pitch solder microbumps are presented in this paper. The aspect ratio of the TSV is larger than 10 and filled with Cu without voids; there are electrical nickel and immersion gold (ENIG) pads on top of the TSV as under bump metallurgy (UBM) layer. On the Si chip, Cu/Sn solder microbumps with 16µm in diameter and 25µm in pitch are fabricated. After singulating the Si chip and the Si carrier, there are joined together and the interconnection is formed between them through the solder micro bumps and the TSV.

Developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies are discussed in this paper. CuSn solder microbumps with 25 mu m in pitch are fabricated at wafer level by electroplating method and the total thicknesses of the platted Cu and Sn are 10um. After plating, the micro bumps oil the Si chip are reflowed at 265 degrees C and the variation of bump height measured within a die is less than 5%. The under bump metallurgy (UBM) layer on the Si carrier used is electroless plated nickel and immersion gold (ENIG) with total thickness less than 5um. Assembly of the Si chip and the Si carrier is conducted with the FC150 flip chip bonder at different temperatures, times, and pressures and the optimized bonding conditions are obtained. After assembly, underfill process is carried out to fill the gap and a void free underfilling is achieved using an underfill material with fine filler size.

This paper focused on design, assembly and reliability assessments of 21 × 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ¿m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97.5Sn2.5Ag), High-Pb (95Pb5Sn) and Cu-post/95Pb5Sn. Two different die thicknesses, such as 750 ¿m and 300 ¿m, were evaluated. the flip chip assembly of high-pb test vehicles required the right choice of flux and special alignment between the high-pb solder bumps and substrate presolder to ensure proper solder bumps and substrate pre-solder alloy wetting. Finite Element Modeling (FEM) was performed to investigate the impact of different underfill, on the inelastic strain of the outermost bumps and shear stress in the Cu/low-K layer. JEDEC standard reliability were performed on the test vehicles with different first level interconnects, die thickness, underfill materials and dicing methods.

With the move to 300 mm wafer, WLP becomes even more attractive as the solution for backend processing. More importantly as an enabling technology for the most advanced 0.13 micron technology using Cu/low-k interconnect devices. Cu/low-k devices need WLP since wire-bond forces could damage the soft device structures. Additionally, low-k interconnect densities often reach values that can only be accommodated by area-array packaging technology. Low-k materials are mechanically, chemically, thermally, and electrically less stable than the historical material of choice, SiO2. Therefore, the challenge lies not only in identifying and characterizing the candidate materials, but also in devising the best method to integrate those materials for packaging. Test wafer was fabricated with 4 Cu/low-k (black diamond) dielectrics layers. And it has multilayer via-chain to check the internal ILD stack reliability. Die size was 15mm times 15mm and IO no. was about 800. Using these test wafers, WLP was fabricated with multidielectrics layers (BCB) and Cu metal redistribution. Wafer level package has 300 mum pitch solder bump and Cu post interconnects to get better board level solder joint reliability. Cu post and solder cap were prepared by electroplating method. To investigate the solder joint integrity, daisy chains are connected to the PCB board and resistance was electrically monitored. Board level solder joint reliability is performed in temperature cycle chamber (-45/120C)