We describe an analysis of the main process parameters variability involved in electrical and optical output characteristics of an optical sensor integrating a standard silicon-based NWell in p-epitaxial substrate photodiode and an UV/IR blocking interference filter. This study is done with TCAD simulation following a standard 0.18 μm high voltage CMOS technology fabrication process. The TCAD simulations combined with specific Design of Experiments permit a better understanding of the main electrical and optical responses variabilities of the optical sensor. This results in an improvement of the inline process control parameters and a better modeling of the sensor for future circuit designs integrating this sensor.

We apply our hot-carrier degradation (HCD) model, which uses the information about the carrier energy distribution, to represent HCD data measured in n- and p-channel LDMOS transistors. In the first version of our model we use the spherical harmonics expansion approach to solve the Boltzmann transport equation (BTE), while in the second version we employ the drift–diffusion scheme. In the latter case the carrier energy distribution function is approximated by an analytic expression with parameters found using the drift–diffusion scheme. The model, which has already been verified with nLDMOS transistors, is used to represent the carrier distribution functions, interface state density profiles, and changes of the drain currents vs. stress time in pLDMOS transistor. Particular attention is paid to study the role of the cold fraction of the carrier ensemble. We check the validity of the model by neglecting the effect of cold carriers in HCD modeling in the case of nLDMOS devices stressed at high voltages. In our model, cold carriers are represented by the corresponding term in the analytic formula for the carrier distribution function as well as by the multiple-carrier process of the Si–H bond dissociation. We show that even in high-voltage devices stressed at high drain voltages the thermalized carriers still have a substantial contribution to HCD.

In this work the influence of nanoscale particles caused by processing excursions during back end of line (BEOL) processing on top of the photodiode active region was examined. To investigate the influence of the particles on the photodiode performance, wafer level optical responsivity measurements were done. In addition to the measurements the effect of the particles was simulated with a simplified model based on a modified transfer matrix method (MTMM)1 . The simulation and measurements are in very good agreement with each other and lead to the conclusion that even though some decrease of sensitivity was observed, the overall system variability was reduced by the presence of particles. Furthermore, the influence of the dielectric stack layer thickness variability on the photon flux density is reduced.

We present two schemes for carrier transport treatment to be used with our hot-carrier degradation (HCD) model. The first version relies on an exact solution of the Boltzmann transport equation (BTE) by means of the spherical harmonics expansion (SHE) method, whereas the second one uses a simplified drift-diffusion (DD) scheme to avoid the computationally expensive SHE approach. We use both versions of the model to simulate the change of the characteristics of an nLDMOS transistor subjected to hot-carrier stress and compare these theoretical degradation traces with the experimental ones. The similarity in the results of the SHE- and DD-based models together with the flexibility of the latter approach makes it attractive for fast and predictive HCD simulations for LDMOS devices.

We propose two different approaches to describe carrier transport in n-laterally diffused MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for our physical hot-carrier degradation (HCD) model. The first version relies on the solution of the Boltzmann transport equation using the spherical harmonics expansion method, while the second uses the simpler drift-diffusion (DD) scheme. We compare these two versions of our model and show that both approaches can capture HCD. We, therefore, conclude that in the case of nLDMOS devices, the DD-based variant of the model provides good accuracy and at the same time is computationally less expensive. This makes the DD-based version attractive for predictive HCD simulations of LDMOS transistors.

We present a physical model for hot-carrier degradation (HCD) which is based on the information provided by the carrier energy distribution function. In the first version of our model the distribution function is obtained as the exact solution of the Boltzmann transport equation, while in the second one we employ the simplified drift-diffusion scheme. Both versions of the model are validated against experimental HCD data in nLDMOS transistors, namely against the change of such device characteristics as the linear and saturation drain currents. We also compare the intermediate results of these two versions, i.e. the distribution function, defect generation rates, and interface state density profiles. Finally, we make a conclusion on the vitality of the drift-diffusion based version of the model.

We model hot-carrier degradation (HCD) in n- and p-channel LDMOS transistors using an analytic approximation of the carrier energy distribution function (DF). Carrier transport, which is an essential ingredient of our HCD model, is described using the drift-diffusion (DD) method. The analytical DF is used to evaluate the bond-breakage rates. As a reference, we also obtain the DF from the solution of the Boltzmann transport equation using the spherical harmonics expansion (SHE) method. The distribution functions and interface state density profiles computed using the SHE and DD-based approaches are compared. The comparison of the device degradation characteristics simulated by these two approaches with the experimental data shows that the DD-based variant, which is considerably less computationally expensive, provides good accuracy. We, therefore, conclude that the DD-based version is efficient for predictive HCD simulations in LDMOS devices.

This paper presents the electrical and optical behavior of Single Photon Avalanche Diode. Key parameters as reverse breakdown voltage, spectral responsivity, photon detection probability, dark count rate and time delay of the diode are extracted from dedicated TCAD simulations.

This work reports the hot-carrier (HC) behavior and specific on-resistance (Ron,sp) optimization of 20~60 V p-channel LDMOS transistors implemented in a 180 nm HV-CMOS technology. By precise control the implant dose and energy of a p-drift region, which is surrounded by n-type isolation well, one can efficiently optimize the on-resistance and breakdown voltage (BV) trade-off while keeping very low HC degradation. Both of the TCAD simulations and measurements are described to explain the proposed technology and the transistor behaviour. Reported p-channel LDMOS transistor (pLDMOS) shows a very low HC-induced degradation - percent change of linear region of drain current (Idlin) below 3 % till 1×105 sec stress), and it shows an excellent Ron,sp-BV trade-off (pLDMOS with 20V GOX: BV = -85 V and Ron,sp = 1.64 mΩ-cm2).

The aim of the work is to develop a statistical SPICE model for the design of high-voltage ICs based TCAD simulations by considering process variations. From the in line data analysis (together with initial TCAD simulations), critical process variables, which are responsible for the electrical parameter shift, have been chosen for process and device TCAD simulations. An interface between commercial process simulator [1] and Minimos-NT [2] (a device simulator developed by TUW) was also addressed, and statistical process and device simulations were performed for the high-voltage n- and p-channel LDMOS transistors implemented in a HV-CMOS technology. Finally, a statistical SPICE model implementation was done successfully as a linear combination of related SPICE parameters.

For competitive high-voltage (HV) integrated circuit (IC) products an excellent trade-off between specific on-resistance Ron,sp and breakdown voltage BV of a HV lateral DMOS (LDMOS) transistor, while keeping low fabrication cost, is mandatory. This paper presents a review of the HVIC technology trend with special emphasis on cost effective 0.35 μm and 0.18 μm HV-CMOS technologies. Through optimized process setup and device engineering a very competitive Ron,sp-BV trade-off of a HV LDMOS transistor without degrading the low-voltage (LV) CMOS performance has been achieved. A 0.35μm HV-CMOS technology with LDMOS transistor operating voltages from 20V to 120V is reported. Only two mask level adders on top of standard CMOS are required to provide the full set of 3.3V, 5V and 20V-120V HV devices. This is the result of taking advantage of predictive TCAD which enables early optimization of device layouts and dopant concentrations. In addition, HV and LV process integration issues of a 0.18 μm HV-CMOS technology, which play a key role to efficiently implement a HV module into a deep submicron CMOS process, are described. Key issues of p-channel LDMOS transistors are reviewed. The hot-carrier (HC) behaviour of a 50 V p-channel LDMOS transistor is presented too.

The interface state density profile for an unstressed transistor has been carefully extracted. The experimental evidence of profile non-uniformity is presented. A scheme to separate the bulk oxide trap contribution from the total charge pumping current is suggested as an improvement to the conventional extraction procedure. The obtained information is of high importance in the context of hot-carrier degradation modeling in order to allow for a more detailed verification of the model.

We develop an analytical model for hot-carrier degradation based on a rigorous physics-based TCAD model. The model employs an analytical approximation of the carrier acceleration integral (calculated with our TCAD approach) by a fitting formula. The essential features of hot-carrier degradation such as the interplay between single-and multiple-electron components of Si–H bond dissociation, mobility degradation during interface state build-up, as well as saturation of degradation at long stress times are inherited. As a result, the change of the linear drain current can be represented by the analytical expression over a wide range of stress conditions. The analytical model can be used to study the impact of device geometric parameters on hot-carrier degradation.