In this work, we experimentally demonstrate monolithic 3-D (M3D) integration of dual-gated (DG) nonvolatile capacitive memory (nvCAP) featuring an ALD W-doped In2O3 (IWO) channel on a foundry 40-nm CMOS chip. We introduce a novel dual-gate engineering scheme for DG nvCAP, effectively addressing the weak erase and poor retention challenges in oxide-channel ferroelectrics (FEs). The BEOL-integrated DG nvCAP on the TSMC N40 CMOS chip achieves a capacitive on-off ratio (C-ON/C-OFF) of similar to 64.4 at V-read=0 V-a record among reported BEOL-compatible nvCAPs. Furthermore, nondestructive read operation exceeding 109 stress cycles at vertical bar V-read vertical bar=1 V is demonstrated in the same device. Finally, we introduce a new "capacitive" digital compute-in-memory (Cap-DCIM) paradigm, achieving 146x higher figure-of-merit (TOPS/W x TOPS/mm(2)) compared with leading analog compute-in-memories (ACIMs) and 111x lower static power versus SRAM-based DCIMs-enabled by highly scalable digital logic and BEOL integration of DG nvCAPs. We experimentally validate the operational principle of M3D Cap-DCIM by demonstrating BEOL capacitance-modulated FEOL Si transistor current amplification through monolithically integrated DG nvCAP on the TSMC N40 CMOS chip.

Computing-in-memory (CIM) architectures offer a promising route toward energy-efficient artificial intelligence by reducing data-movement overhead. However, most existing CIM hardware operates at a fixed trade-off between accuracy, energy efficiency, and robustness, limiting adaptability to diverse workloads. Here, we present a dual-mode CIM accelerator based on an AND-type charge-trap flash array that enables energy-adaptive operation without device-level structural modification. By integrating transistor-mode current sensing and capacitor-mode charge sensing in the same device structure, the proposed architecture allows flexible switching between high-precision computation and ultra-low-power, noise-resilient operation within a single hardware platform through peripheral switching associated with each sensing mode. Experimental results demonstrate reliable vector-matrix multiplication, hardware neural network inference, and strong tolerance to device and voltage variations. System-level benchmarking further confirms improved energy efficiency and reduced peripheral overhead. This work establishes a practical and scalable CIM platform that dynamically balances performance and robustness, providing a versatile foundation for energy-adaptive artificial intelligence (AI) hardware.

The Last Level Cache (LLC) is the processor's critical bridge between on-chip and off-chip memory levels - optimized for high density, high bandwidth, and low operation energy. To date, high-density (HD) SRAM has been the conventional device of choice; however, with the slowing of transistor scaling, as reflected in the industry's almost identical HD SRAM cell size from 5 nm to 3 nm, alternative solutions such as 3D stacking with advanced packaging (i.e., hybrid bonding) are pursued (as demonstrated in AMD's V-cache). Escalating data demands necessitate ultra-large on-chip caches to decrease costly off-chip memory movement, pushing the exploration of device technology towards monolithic 3D (M3D) integration, where transistors can be stacked in the back-end-of-line (BEOL) at the interconnect level. M3D integration requires fabrication techniques compatible with a low thermal budget (< 400 degrees C). Among promising BEOL device candidates are amorphous oxide semiconductor (AOS) transistors, particularly desirable for their ultra-low leakage (< fA/mu m), enabling persistent data retention (> seconds) when used in a gain-cell configuration. This paper examines device, circuit, and system-level tradeoffs made when optimizing BEOL-compatible AOS-based 2-transistor gain cells (2T-GC) for LLC. A cache early-exploration tool, NS-Cache, is developed to model caches in advanced 7 & 3 nm nodes and is integrated with the Gem5 simulator to systematically benchmark the impact of the newfound density/performance when compared to HD-SRAM, MRAM, and 1T1C eDRAM alternatives for LLC.

The rapid growth of Ethereum has made it more important to quickly and accurately detect smart contract vulnerabilities. While machine-learning-based methods have shown some promise, many still rely on rule-based preprocessing designed by domain experts. Rule-based preprocessing methods often discard crucial context from the source code, potentially causing certain vulnerabilities to be overlooked and limiting adaptability to newly emerging threats. We introduce BugSweeper, an end-to-end deep learning framework that detects vulnerabilities directly from the source code without manual engineering. BugSweeper represents each Solidity function as a Function-Level Abstract Syntax Graph (FLAG), a novel graph that combines its Abstract Syntax Tree (AST) with enriched control-flow and data-flow semantics. Then, our two-stage Graph Neural Network (GNN) analyzes these graphs. The first-stage GNN filters noise from the syntax graphs, while the second-stage GNN conducts high-level reasoning to detect diverse vulnerabilities. Extensive experiments on real-world contracts show that BugSweeper significantly outperforms all state-of-the-art detection methods. By removing the need for handcrafted rules, our approach offers a robust, automated, and scalable solution for securing smart contracts without any dependence on security experts.

Ferroelectric non-volatile capacitor (nvCAP) device is a new candidate for charge-domain computing. The impact of process variation (PV) is yet to be quantified. This work presents a physics-informed neural network (PINN)-assisted compact model that accurately captures effects under PV parameters for scaled nvCAP devices, demonstrating superior physical accuracy when trained on sparse training data compared to a purely data-driven neural network model. Array-level simulations reveal that PV-induced variations cause the effective number of bits (ENOB) variation to 20%, making tight process control crucial for reliable operation. This work highlights the advantages of PINN-assisted compact modeling in assessing PV-induced reliability predictions for emerging devices.

Social graph-based fake news detection aims to identify news articles containing false information by utilizing social contexts, e.g., user information, tweets and comments. However, conventional methods are evaluated under less realistic scenarios, where the model has access to future knowledge on article-related and context-related data during training. In this work, we newly formalize a more realistic evaluation scheme that mimics real-world scenarios, where the data is temporality-aware and the detection model can only be trained on data collected up to a certain point in time. We show that the discriminative capabilities of conventional methods decrease sharply under this new setting, and further propose DAWN , a method more applicable to such scenarios. Our empirical findings indicate that later engagements (e.g., consuming or reposting news) contribute more to noisy edges that link real news-fake news pairs in the social graph. Motivated by this, we utilize feature representations of engagement earliness to guide an edge weight estimator to suppress the weights of such noisy edges, thereby enhancing the detection performance of DAWN . Through extensive experiments, we demonstrate that DAWN outperforms existing fake news detection methods under real-world environments. The source code for DAWN is available at https://github.com/LeeJunmo/DAWN .

Physics-based compact modeling requires substantial work to formulate equations and fine-tune coefficients. In this work, we propose a machine learning (ML)-assisted compact model to capture alternating current (AC)-induced positive bias temperature instability (PBTI) in top-gate indium tungsten oxide (IWO) transistors, demonstrating high accuracy (R-2= 0.94 similar to 0.98) across various operating conditions. Aging simulations of 2T gain cell (GC) embedded DRAM (eDRAM) reveal that the write transistor is more vulnerable to AC stress, leading to data hold failures as the number of AC cycles increases. This study highlights the advantages of ML-assisted compact modeling in improving reliability predictions for emerging semiconductor devices.

This article presents a machine learning (ML)-assisted compact modeling framework to analyze and mitigate bias temperature instability (BTI) under alternating current (ac) stress in oxide semiconductor-channel transistors, with a focus on 2T gain cell (GC) embedded DRAM (eDRAM) applications. We investigate top-gate (TG) and bottom-gate (BG) indium tungsten oxide (IWO) transistors, fabricated using a low-temperature process suitable for back-end-of-line (BEOL) integration. Experimental results reveal distinct aging mechanisms under ac stress: TG transistors exhibit a negative threshold voltage shift (Delta V-T), while BG transistors show a positive Delta V-T. These differences lead to unique failure modes in eDRAM circuits. To address this issue, we propose a hybrid 2T GC eDRAM design that combines BG IWO for write operations and TG IWO for read operations to enhance reliability. The ML-assisted BTI model with experimental data accurately predicts Delta V-T across diverse conditions-frequency, temperature, duty cycle (DT), and overdrive voltage. Circuit-level simulations of the proposed hybrid 2T GC eDRAM demonstrate reliable operation up to one billion read/write cycles.

Digital compute-in-memory (DCIM) has emerged as a promising solution to address scalability and accuracy challenges in analog compute-in-memory (ACIM) for next-generation AI hardware acceleration. In this work, we present a comprehensive device-to-system codesign process for the two proposed 3-D DCIM architectures at the projected 5 angstrom (A5) complementary FET (CFET) technology node: 1) 3-D DCIM based on 8T DCIM bit cell and 2) lookup-table (LUT)-based 3-D DCIM. A novel A5 CFET-based 8T DCIM bit cell (6T SRAM +2T AND gate) is proposed to improve total footprint and latency over the conventional 10T DCIM bit cell, and its functionality is verified through technology computer-aided design (TCAD) simulation. For macro- and system-level evaluation of the proposed 3-D DCIM architectures, an extended NeuroSim V1.4 framework is developed, the first compute-in-memory (CIM) benchmark framework enabling CIM simulation at the A5 CFET technology node. We demonstrate that the proposed 3-D DCIM with 8T DCIM bit cell at the A5 CFET technology node can achieve 8.2 x improvement in figure of merit (FOM) (=TOPS/W x TOPS/mm(2)) over the state-of-the-art 3-nm FinFET-based DCIM design. The LUT-based 3-D DCIM design is additionally proposed to achieve further power consumption reduction from the 8T DCIM bit-cell-based 3-D DCIM. LUT-based 3-D DCIM achieves a 44% reduction in energy consumption compared to the conventional 10T DCIM bit-cell-based 3-D DCIM. Our findings suggest the significant implications for technology scaling below 1 nm in high-performance DCIM design.

We experimentally demonstrate monolithic 3D (M3D) integration of dual-gated (DG) non-volatile capacitive memory (nvCAP) featuring an ALD W-doped In2O3 (IWO) channel on a TSMC N40 CMOS foundry chip. Key technical advancements include: i) Novel dual-gate engineering of nvCAP, effectively addressing the weak erase and poor retention challenges with oxide-channel ferroelectrics; ii) First successful BEOL integration of DG nvCAP on a foundry CMOS chip, achieving a non-destructive capacitive on/off ratio of similar to 64.4 at V-read=0 V-a record among reported BEOL-compatible nvCAPs; iii) Non-destructive read endurance exceeding 10(9) cycles at vertical bar V-read vertical bar=1 V, achieved in BEOL-integrated DG nvCAPs; iv) Introduction of the M3D non-destructive "capacitive" digital-compute-in-memory (Cap-DCIM) paradigm, achieving 146x higher figure-of-merit (TOPS/WxTOPS/mm(2)) compared to leading analog CIMs and 111x lower static power versus SRAM-based DCIMs-enabled by highly scalable digital logic and BEOL integration of DG nvCAPs. Finally, we experimentally validate the operational principle of M3D Cap-DCIM, by demonstrating BEOL capacitance-modulated FEOL Si transistor current amplification through monolithically integrated DG nvCAP on a foundry CMOS chip. These advancements offer a promising pathway to overcome the long-standing scalability and variability limitations of leading analog CIM approaches.

The increasing demand for energy-efficient computing has created the need for advanced power management solutions. Backside power delivery network (BSPDN) has been introduced in the industry for 2-nm node with passive wires. In this work, we propose adding active components (power transistors) to the backside of silicon in a back-end-of-line (BEOL)-compatible fabrication process. The goal is to enable 12-0.7-V voltage downconversion at the backside of silicon (near the point of load, i.e., the frontside logic compute die) to minimize the IR drop and improve overall system-level conversion efficiency. This work leverages a hybrid monolithic 3-D (M3D)dc-dc converter architecture combining switched-capacitor (SC) and synchronous buck converter topologies with BEOL-compatible active and passive devices. The design employs amorphous tungsten-doped indium oxide (IWO) transistors, which offer high breakdown voltage and tunable threshold voltages, supporting both enhancement and depletion modes for efficient switching. With the experimentally calibrated compact models, the simulated hybrid converter design achieves 12-0.7-V conversion with a peak efficiency of 95.6% at a power density of 330 mW/mm(2), demonstrating the feasibility of M3D SC dc-dc converters for next-generation power management in high-performance edge devices.

This work presents a breakthrough in on-chip point-of-load (PoL) DC-DC voltage conversion for heterogeneous 3D integrated circuits by leveraging BEOL-compatible transistor and trench capacitor architectures. This work presents indium-tin-oxide (ITO) planar transistors and vertical indium-gallium-oxide (IGO) transistors, achieving a specific on-resistance of 87 and 0.04 m Omega.mm(2) for 12V and 3V voltage ratings, respectively. 3D trench Hf0.25Zr0.75O2 flying capacitors with 97.9 fF/mu m(2) capacitance density are demonstrated. By monolithically integrating enhancement- and depletion-mode ITO planar transistors, a 2:1 switched-capacitor DC-DC converters are experimentally demonstrated with >= 87.5% efficiency per stage. Circuit simulations using IGO vertical transistors and 3D trench Hf0.25Zr0.75O2 capacitors exhibit 94.3% peak stage efficiency for 2:1 step-down conversion from 3 V, offering competitive BEOL-compatible active and passive device technologies for "active" backside power delivery.

The resistive crossbar with a feedback loophas been proposed for solving matrix equations in a lin-ear system with the current-domain computation. But theresistive approach suffers from high static power especiallywhen the resistance is low. To overcome the challenges,we leverage C-V asymmetry in the ferroelectric capacitorsof a crossbar array for the energy-efficient charge-domaincomputation. In this work, we demonstrate that such acapacitive crossbar when operated in negative feedbackcould solve the matrix problem Ax=bwherexis theunknown vector. A comparative study shows a much lowerpower consumption (similar to 1000x) for such a matrix solverwhen compared to the resistive crossbar counterpart

Social graph-based fake news detection aims to identify news articles containing false information by utilizing social contexts, e.g., user information, tweets and comments. However, conventional methods are evaluated under less realistic scenarios, where the model has access to future knowledge on article-related and context-related data during training. In this work, we newly formalize a more realistic evaluation scheme that mimics real-world scenarios, where the data is temporality-aware and the detection model can only be trained on data collected up to a certain point in time. We show that the discriminative capabilities of conventional methods decrease sharply under this new setting, and further propose DAWN, a method more applicable to such scenarios. Our empirical findings indicate that later engagements (e.g., consuming or reposting news) contribute more to noisy edges that link real news-fake news pairs in the social graph. Motivated by this, we utilize feature representations of engagement earliness to guide an edge weight estimator to suppress the weights of such noisy edges, thereby enhancing the detection performance of DAWN. Through extensive experiments, we demonstrate that DAWN outperforms existing fake news detection methods under real-world environments. The source code is available at https://github.com/LeeJunmo/DAWN.

Non-volatile capacitive memories (nvCAPs) exhibiting AC small-signal capacitance on/off ratio (Con/Coff) with non-destructive read have emerged as a promising device for next-generation memory paradigms. Recently, BEOL-compatible ferroelectric nvCAPs with an amorphous oxide semiconductor channel have been reported, suggesting the possibility of monolithic 3D integration of nvCAPs on top of CMOS. So far, the characterization studies on oxide-channel ferroelectric nvCAPs have been done using dual DC sweep C-V measurements which are typically performed over a time scale of a few seconds. However, non-volatile memory arrays typically require nvCAPs to operate under pulse-mode. It is thus crucial to advance understanding of the behavior of oxide-channel ferroelectric nvCAPs under pulse-mode operation, governed by the unique interplay between ferroelectric layer and oxide channel physics. In this study, we provide a systematic study of the pulse-mode operation of ferroelectric nvCAPs with an amorphous oxide semiconductor channel, including its pulse-based write characteristics and reliability characteristics. We examine overlap area, wake-up and pulse-width dependent Con and Coff writing characteristics under pulse-mode. Further, we suggest the importance of optimizing ferroelectric depolarization for Con retention, while reducing read-after-delay for Coff retention under pulse-mode. Lastly, non-destructive read operation for >10^9 read stress cycles at |Vread|=1V is demonstrated.

In this work, we experimentally demonstrate a charge-domain Ternary Content Addressable Memory (TCAM) array using back-end-of-line (BEOL) compatible ferroelectric non-volatile capacitors (nvCAPs) for in-memory search. The TCAM cell consists of two nvCAPs to store bit ('0, 1, X), and an additional nvCAP for charge cancellation to increase the output swing and perform error correction. BEOL-compatible nvCAPs are fabricated using 3.5nm ALD deposited W-doped In2O3 (IWO) and 7nm Hf0.5Zr0.5O2 ( HZO). The geometrically optimized nvCAP provides: 1) reduced static power consumption due to charge-domain compute with charge-transfer mechanism, 2) non-destructive readout with a 100mV pulse, 3) >1000s (or 1012 equivalent read cycles) read-stress resilience and retention @85 degrees C temperature. The pattern matching measurements and linear dependence of output response of TCAM array on the level of similarity between stored and searched pattern are conducted for the functional verification of TCAM array. The proposed TCAM is evaluated for bioinformatic workloads in genome sequencing by performing SPICE and system-level simulation. The benchmarking for scaled nvCAP devices exhibits similar to 40x improvement in search energy-delay-product over the conventional 16T CMOS TCAM implementations.

In this letter, a ferroelectric field effect transistor (FeFET)-based charge-domain ternary content addressable memory (TCAM) is experimentally demonstrated for in-memory search. Specifically, foundry based FeFETs are configured in non-volatile capacitor (nvCAP) mode for charge-domain computation. A single TCAM cell consisting of 2 nvCAPs (i.e. two FeFETs) is used to perform the Store: bit '0', '1', 'X' and Search: bit '0', '1', 'X' operations. Further, SPICE simulations are performed to evaluate the feasibility of a scaled nvCAP device in a large TCAM array. The low C ON /C OFF ratio of a scaled device can lead to false-positive matchings, which can be countered by introducing a dummy column and input dependent charge cancellation. Finally, the charge-domain nvCAP TCAM is benchmarked against other proposed candidates, showing a similar to 1.5x improvement in energy efficiency over FeFET based current domain TCAM, and a similar to 3.3x improvement compared to resistive random access memory (RRAM) based TCAM.

Ferroelectric field-effect transistors (FeFETs)-based vertical NAND (Fe-VNAND) has emerged as a promising solution to z-scaling limitations of conventional charge trap layer (CTL)-based VNAND (Fig. 1) with reduced programming voltage (from $\gt30 \mathrm{~V}$ to $(\lt)15 \mathrm{~V}$) [1]. Band engineered FeFETs are actively being explored to enable multilevel (3-bit per cell) operations [2, 3]. Although the gate blocking layer (GBL) allows higher memory window (MW>7 V) [4], it suffers from poor retention characteristics [5] which lead to more sophisticated gate stack engineering by inserting Al2O3 tunnel dielectric layer (TDL) in the middle of FE stacks (Hf0.5Zr0.5O2(HZO)) to achieve high MW and robust retention (Fig. 2) [4 –6]. In this paper, a comprehensive TCAD-based analysis of interlayer gate stack engineering is performed to understand time-dependent interplay between charge trapping and polarization, as well as the impact of ferroelectric/dielectric phase variations. This dynamic modeling approach is crucial for guiding effective gate stack design in Fe-VNAND applications.

As artificial intelligence (AI) continues to permeate various domains, concerns surrounding trust and transparency in AI-driven inference and training processes have emerged, particularly with respect to potential biases and traceability challenges. Decentralized solutions such as blockchain have been proposed to tackle these issues, but they often struggle when dealing with large-scale models, leading to time-consuming inference and inefficient training verification. To overcome these limitations, we introduce BRAIN, a Blockchain-based Reliable AI Network, a novel platform specifically designed to ensure reliable inference and training of large models. BRAIN harnesses a unique two-phase transaction mechanism, allowing real-time processing via pipelining by separating request and response transactions. Each randomly-selected inference committee commits and reveals the inference results, and upon reaching an agreement through a smart contract, then the requested operation is executed using the consensus result. Additionally, BRAIN carries out training by employing a randomly-selected training committee. They submit commit and reveal transactions along with their respective scores, enabling local model aggregation based on the median value of the scores. Experimental results demonstrate that BRAIN delivers considerably higher inference throughput at reasonable gas fees. In particular, BRAIN's tasks-per-second performance is 454.4293 times greater than that of a naive single-phase implementation.