Utilizing the Ferroelectric FET (FeFET) technology as a capacitive element in charge-based in-memory computing (IMC) arrays offers multiple advantages over the classical current-based computing, such as reduced read disturbances and negligible static power. However, traditional variation sources and reliability concerns tied to FeFET devices that challenge their applicability remain a question for non-volatile capacitor (nvCap) mode FeFET arrays. Crucially, we present a comprehensive device-to-system level comparison, demonstrating the reliability and accuracy of FeFET charge-based computing over the conventional current-based approach in the presence of variability. Device-level reliability analyses conducted experimentally using measurements from FeFET devices fabricated in a 28 nm technology platform, and additionally through TCAD simulations, reveal superior resilience against variability for the nvCap with a 0.66% σ/μ ratio for the on-state capacitance. At the circuit level, a novel 8-bit ADC array with ~90.0% accuracy was realized thanks to the reduced variability by operating the FeFET in nvCap mode. Injecting the error into our charge-based HDC model for language classification results in an average inference accuracy loss of <0.2 percentage points, while the current-based version loses as much as 5.7 percentage points.

This study investigates the short-term (mu s to s timespan) charge trapping effects in hafnium oxide-based ferroelectric field-effect transistors, integrated within GlobalFoundries' 28 nm bulk high-k metal gate (HKMG) technology. Even without ferroelectric switching, positive gate voltage pulses can cause significant short-term electron trapping due to strong energy band bending that enables charge injection. A systematic analysis reveals that the extent of short-term trapping increases with both the amplitude and the duration of the applied gate pulses. These dependencies are consolidated into a positive bias charge trapping matrix, offering an overview of how various factors collectively influence trapping behavior. Negative gate bias does not cause charge trapping in FeFETs for the investigated voltage and time domain. Building on previous reports of degradation-free unipolar endurance cycling, these observations further support the conclusion that the pronounced short-term trapping effects are primarily non-destructive. The study highlights the importance of understanding and accounting for short-term charge trapping effects, especially as they relate to read-after-write capabilities and overlaps with switching mechanisms. This understanding is crucial for optimizing the consistent and effective operation of FeFETs as memory cells and neuromorphic computing elements.

Time-domain nonvolatile in-memory computing (TD-nvIMC) offers a promising pathway to reduce data movement and improve energy efficiency by encoding computation in delay rather than voltage or current. This work presents a fully integrated and reconfigurable TD-nvIMC macro, fabricated in 28 nm CMOS, that combines a ferroelectric FET (FeFET)-based content-addressable memory array, a cascaded delay element chain, and a time-to-digital converter. The architecture supports binary multiply-and-accumulate (MAC) operations using XORand AND-based matching, as well as in-memory Boolean logic and arithmetic functions. Sub-nanosecond MAC resolution is achieved through experimentally demonstrated 550 ps delay steps, representing a 2000 & times; improvement over prior FeFET TD-nvIMC work, enabled by multilevel-state calibration with <= 100 ps resolution. Write-disturb resilience is ensured via isolated triple-well bulks. The proposed macro achieves a measured throughput of 222.2 MOPS/cell and energy efficiency of 1887 TOPS/W at 0.85 V, establishing a viable path toward scalable, energy-efficient TD-nvIMC accelerators.

Localization of random ferroelectric (FE) domain distribution and interface trap density $(\mathrm{D}_{\text{IT}})$ in the ferroelectric field effect transistor (FeFET) is identified as a new challenge for enabling robust Multi-Level Cell (MLC) operation. FE localization leads to dynamic dependence of $\mathrm{V}_{\text{TH}}$ on the $\mathrm{V}_{\text{DS}}$, leading to read-out errors using the classical notion of utilizing $\mathrm{V}_{\text{TH}}$ distribution as the criteria for MLC. This work presents a new MLC scheme that utilizes the dynamic drive strength of FeFET, featuring a characteristic time constant $\tau$ to discharge the bitline as a more appropriate MLC criteria. Key contributions include: 1) Experimental statistical characterization of scaled FeFET on 28 nm Foundry platform for classical and new MLC schemes; 2) First report of $\mathrm{D}_{\text{IT}}$ localization that exhibits a “crossover” effect in $\mathrm{I}_{\mathrm{D}}-\mathrm{V}_{\mathrm{G}}$ characteristics; 3) Modelling of FE and $\mathrm{D}_{\text{IT}}$ localization; 4) Validation of the new MLC scheme showing minimized errors across a dynamically varying bitline voltage swing.

Ferroelectric-based capacitive crossbar arrays have been proposed for energy-efficient in-memory computing in the charge domain. They combat the challenges like sneak paths and high static power faced by resistive crossbar arrays but are susceptible to thermal noise limiting the effective number of bits (ENOBs) for the weighted sum. A direct way to reduce this thermal noise is by lowering the temperature, as thermal noise is proportional to temperature. In this work, we first characterize the nonvolatile capacitors (nvCAPs) on a foundry 28-nm platform at cryogenic temperatures to evaluate the memory window (MW), on state retention as a function of temperature down to 77 K, and then use the calibrated device models to simulate the capacitive crossbar arrays in SPICE at lower temperatures to demonstrate higher ENOB (similar to 5 bits) for 128 & times; 128 multiply-and-accumulate (MAC) operations.

Threshold voltage variability is a key concern in ferroelectric field effect transistor (FeFET) technology. In this work, a study spanning experiments, modeling, and SPICE simulations is conducted to evaluate the impact of localized FE/ dielectric (DE) distributions on the threshold voltage ( V-TH ) of FeFET. The device characterization is performed on the 28-nm FeFET foundry platform. The experimental study on device-to-device (D2D) and cycle-to-cycle (C2C) variations reveals that the FeFET can be an asymmetric device, with the VTH showing dependence on the direction of current flow, as well as the magnitude of applied drain voltage ( V-DS ) to the device. The TCAD modeling study reveals that the cause of asymmetry is the spatial localization of DE phases that may occur due to the random nature of the distribution. SPICE simulation for two-FeFET-based ternary content-addressable memory (TCAM) reveals that as few as two devices exhibiting the localization-induced threshold voltage shift can lead to a 64-bit search failure. Various strategies are investigated to minimize the impact of such localized phase distribution-induced threshold voltage shift (LPTS) effect. Notably, the capacitive readout of FeFET and the insertion of a floating metal electrode in the gate-stack improve the robustness.

Symbol decoding in multiple-input multiple-output (MIMO) wireless communication systems requires the deployment of fast, energy-efficient computing hardware deployable at the edge. The brute-force and exact maximum likelihood (ML) decoder, solved on conventional classical digital hardware to decode MIMO symbols, has exponential time complexity. Approximate classical solvers implemented on the same hardware have polynomial time complexity at the best. In this article, we design an alternative ring-oscillator-based coupled oscillator array (also known as oscillatory neural network) to act as an oscillator Ising machine (OIM) and heuristically solve the ML-based MIMO detection problem. Complementary metal oxide semiconductor (CMOS) technology is used to design the ring oscillators, and ferroelectric field effect transistor (FeFET) technology is chosen as the non-volatile memory (NVM) coupling element (X) between the oscillators in this CMOS + X OIM design. For this purpose, we experimentally report high linear range of conductance variation (1-60 & micro;S) with programming voltage pulses in a HfO2-based FeFET device fabricated at 28 nm high-K/ metal gate CMOS technology node. We incorporate the conductance modulation characteristic in SPICE simulation of the ring oscillators connected in an all-to-all fashion through a crossbar array of these FeFET devices. We show that the above range of conductance variation of FeFET is suitable to obtain best OIM performance, thereby making FeFET a suitable NVM device for this application. Our SPICE simulations show that there is no significant performance drop for symbol detection up to MIMO array sizes of 90 transmitting and 90 receiving antennas. Our simulations, combined with analytical treatment using Kuramoto model of oscillators, predict that this designed classical analogue OIM, if implemented experimentally, will offer logarithmic scaling of computation time with MIMO size, thereby offering huge improvement (in terms of computation speed) over exact and approximate classical solvers run on conventional digital hardware.

Artificial intelligence applications in autonomous driving, medical diagnostics, and financial systems increasingly demand machine learning models that can provide robust uncertainty quantification, interpretability, and noise resilience. Bayesian decision trees (BDTs) are attractive for these tasks because they combine probabilistic reasoning, interpretable decision-making, and robustness to noise. However, existing hardware implementations of BDTs based on CPUs and GPUs are limited by memory bottlenecks and irregular processing patterns, while multi-platform solutions exploiting analog content-addressable memory (ACAM) and Gaussian random number generators (GRNGs) introduce integration complexity and energy overheads. Here we report a monolithic FDSOI-FeFET hardware platform that natively supports both ACAM and GRNG functionalities. The ferroelectric polarization of FeFETs enables compact, energy-efficient multi-bit storage for ACAM, and band-to-band tunneling in the gate-to-drain overlap region and subsequent hole storage in the floating body provides a high-quality entropy source for GRNG. System-level evaluations demonstrate that the proposed architecture provides robust uncertainty estimation, interpretability, and noise tolerance with high energy efficiency. Under both dataset noise and device variations, it achieves over 40

Aerial search and rescue missions require fast and reliable victim detection under uncertain and rapidly changing environments. Deterministic deep learning models can produce overconfident false positives, forcing unmanned aircraft systems to perform costly verification maneuvers that reduce search coverage and increase rescue delay. Bayesian neural networks provide uncertainty-aware detection, but their sampling overhead is challenging for battery-constrained edge platforms. This work presents a FeFET-based Bayesian inference engine with a write-free central limit theorem Gaussian random number generator embedded in a compute-in-memory macro. By summing currents from a randomly selected subset of minimum-sized, programmed-once FeFETs, the proposed architecture eliminates energy- and endurance-intensive write operations during inference while maintaining scalable Gaussian sampling. The CLT-GRNG consumes 640 aJ per sample, providing a 560x energy-efficiency improvement over prior BNN accelerators, while the CIM tile achieves 185 TOPS/W/mm2. Evaluated on aerial search and rescue detection, the Bayesian model improves uncertainty calibration and robustness under environmental corruption, reducing risk and enabling low-confidence detections to be filtered before costly verification. These results demonstrate an energy-efficient and uncertainty-aware edge AI engine for autonomous search and rescue systems.

Ferroelectric field-effect transistors (FeFETs) are strong candidates for synaptic devices in neuromorphic and in-memory computing due to their multi-level programmability, non-volatility, and complementary metal-oxide-semiconductor (CMOS) compatibility. In this work, we experimentally demonstrate multi-bit operation of FeFET synapses integrated on GlobalFoundries’ 28nm CMOS process. Specifically, the work uses an incremental pulsing scheme, showing stable access to intermediate polarization states and long-term retention. We further examine the role of device size, read-out gate voltage, and array topology as fundamental design trade-offs, showing that larger-area FeFETs provide more deterministic state programming, while smaller devices favor integration density. Finally, we compare 1-FeFET and nT–1FeFET array architectures with static random-access memory (SRAM), outlining the density, selection, and scalability implications of each. These findings provide both device-level insights and circuit-architecture considerations, guiding the co-design of FeFET-based synaptic arrays for future neuromorphic accelerators.

Understanding charge trapping mechanisms and characterizing oxide traps in hafnium oxide (HfO2)-based ferroelectric field-effect transistors (FeFETs) is essential for addressing long read-after-write (RAW) delays and limited endurance, two key challenges hindering their adoption. In this work, we employ random telegraph noise (RTN) measurements under varying programming and polarization conditions to investigate their impact on charge trapping. We find that introducing a preliminary negative (erase) gate voltage pulse before a positive (program) pulse significantly alters the observed RTN signal, suggesting that distinct trap energies or spatial locations are activated following erase. By contrast, RTN after a positive-only program pulse exhibits highly repeatable behavior. Analysis of capture and emission time constants enables the extraction of trap energies, consistent with previously reported values in similar devices. Finally, we discuss the inherent limitations of RTN for comprehensive trap characterization. These insights advance the understanding of defect behavior in FeFETs and their role in device reliability.

Time-domain circuits are emerging as a key approach for high-speed and energy-efficient data conversion. Among them, voltage-to-time converters (VTCs) serve as the core interface between analog voltages and time-encoded signals. However, conventional VTCs are highly sensitive to process, temperature, and supply variations, often requiring extensive calibration and compensation circuits that increase area and power. This work presents a ferroelectric FET (FeFET)-based tunable VTC, where the programmable polarization of the FeFETs adjusts its threshold voltage, enabling operation as a tunable current source. This resulting tunability allows post-fabrication control of gain, linearity, and timing precision with minimal overhead. A prototype in 28 nm CMOS demonstrates adjustable delays from 1.8 ns to 6 ns, a linear input range of 0.3-1.05 V, a programmable gain of 1-5.1 ns/V, and consumes $0.7~\mu \mathrm{W}$ at 500 MHz from a $0.85-\mathrm{V}$ supply, achieving an energy efficiency of 1.4 fJ/conversion, while maintaining a compact area of $6.07~\mu m^{2}$.

In this work, gate metal work function $(\Phi_{\mathrm{M}}$) engineering is employed to probe the switching dynamics in hafnium zirconium oxide (HZO)-based n-type ferroelectric field-effect transistors (FeFETs) with gate-side injection (GSI), targeting reliable 3D NAND storage. We show that switching behavior is governed by charge trapping during program/erase and post-pulse detrapping, both strongly modulated by the gate metal $\Phi_{\mathrm{M}}$. Four key observations are identified: (i) switching is jointly determined by charge trapping and subsequent detrapping; (ii) without detrapping, lower $\Phi_{\mathrm{M}}$ gates enhance GSI, resulting in larger threshold voltage $(\mathrm{V}_{\text{TH}}$) shifts or earlier switching onset at a given write voltage; (iii) after erase, lower $\Phi_{\mathrm{M}}$ gates experience increases GS electron detrapping during the delay, requiring higher write voltages to compensate charge loss; (iv) after programming, enhanced injection and polarization from the lower $\Phi_{\mathrm{M}}$ gates increase the electric field at the channel-side (CS) interlayer, suppressing CS electron detrapping. The results show that GSI FeFETs with evaporated aluminum gates exhibit higher onset voltages $(\mathrm{V}_{\text{ERS }}=-9 ~\mathrm{V}$ and $\mathrm{V}_{\text{PGM }}=10 ~\mathrm{V}$), higher DC breakdown voltages (-11.5 V), and superior disturb immunity $(\Delta \mathbf{V}_{\mathbf{T H}} \approx 0$ after 105 cycles at $\mathrm{V}_{\text{PASS }}=\mathbf{7 V}$).

This work presents a comprehensive investigation of the abnormal increase of subthreshold swing (SS) from room to cryogenic temperatures. We experimentally demonstrate that (1) the increase of SS (iSS) occurs as temperature decreases beyond a certain point in poly-Si and amorphous oxide transistors, and (2) the onset temperature of the iSS strongly depends on the drain bias and device geometry (i.e., $\mathrm{W}_{\text{ch}} / \mathrm{L}_{\text{ch}}$). Furthermore, a physics-based compact model is developed for capturing the behavior of iSS from $\mathbf{3 0 0 K}$ to $\mathbf{4 K}$. The experimentally observed iSS is an artifact caused by the measuring instrument's limit.

In this article, the impact of the measurement delay and connection to the body contact on the reliability of the ferroelectric field effect transistor (FeFET) under the capacitive nondestructive read mode is studied. Specifically, the endurance characteristics of the FeFET’s gate-to-source/drain capacitance are analyzed. The study is performed on 28-nm bulk Si FeFET technology, with body contact either grounded or floating. We find that the FeFET device exhibits an erase after program delay, where as the number of pulses during the bipolar stress increases, the ferroelectric switching of the FeFET reduces. During the memory window (MW) evaluation (after the bipolar stress), the system setup delays are longer than the erase after program delay in the actual operation. Hence, the ferroelectric switching is restored showing a full MW. The results indicate that the presence of this erase after program delay imposes a minimum stress frequency on the device, which in turn increases the measurement time. Furthermore, the result points toward the need to re-evaluate the standard endurance measurement practice.

In this work, we present comprehensive experimental and modeling studies addressing the challenges of our previously proposed dual-port ferroelectric FET (FeFET) architecture for pass disturb-free vertical NAND storage. This architecture incorporates a string-compatible independent pass gate within the string core, which is dedicated for pass operation rather than relying on the same write gate. Our key findings are as follows: i) The non-ferroelectric pass gate ensures pass disturb immunity via its geometry—pass voltage aids retention of the high-threshold voltage (HVT) state, while the its adverse influence on the low-threshold voltage (LVT) state is effectively screened by the channel; ii) A critical challenge is the increased leakage current in the HVT state, attributed to a weak back-channel region not fully depleted by the front gate, which is verified via both TCAD modeling and experimental demonstration; iii) To mitigate this, we explore the design space of the pass gate oxide and channel thickness through TCAD simulations, and experimentally validate the modeling using dual-port gate-side injection (GSI) FeFETs; iv) The example design, when implemented, demonstrates pass disturb-free operation while effectively managing the leakage trade-off; v) Another challenge is reduced ON-current for LVT state when unselected cells remain in HVT states. This can be mitigated by applying proper pass gate biases.

FeFET technology offers the potential for fast, energy-efficient, low-cost, and high-capacity non-volatile memory and neuromorphic devices. However, charge trapping significantly affects device operation, leading to issues like read-after-write delay and limited endurance. Therefore, a detailed understanding of charge trapping, charge origin and its role in polarization switching is crucial. In this study, we uncover the spectral energy origin of polarization charges in Si:HfO2 N-FeFET by probing electron (conduction band) and hole (valence band) currents separately during polarization-voltage (P-V) measurements. We utilize a fast (similar to 20 ns) and modified positive-up- negative-down (PUND) technique, where bulk, source, and drain currents of the FeFET are measured separately. The nanosecond timescale of the measurement results in measurable currents in FeFETs having dimensions of a few mu m. This charge separation shows that program (PRG, V-GS > 0) charge originates from the conduction band, whereas erase (ERS, V-GS < 0) originates from the valence band of the Si. Moreover, the polarization curve (P-V) of a cycled device (following 5000 PRG/ERS pulses) shows measurable hysteresis even though the transfer curve of the same device shows that the memory window in the threshold voltage vanishes. Therefore, the FeFET polarization state can be read without delay after write operation by the fast PUND measurement, both for pristine and cycled FeFETs.

Phase variations in the ferroelectric thin films are the primary cause of the threshold voltage (VTH) variation in the Ferroelectric Field Effect Transistor (FeFET). In this work, the impact of "localized" ferroelectric/dielectric (FE/DE) phase variation on FeFET is evaluated. A new phenomenon, namely, Localized Phase Distribution Induced Threshold Voltage Shift (LPTS), is experimentally characterized. Here, a scaled FeFET exhibits an asymmetric current readout that leads to a threshold voltage (VTH) shift that is dependent on the direction of current flow (when source and drain are flipped). The device characterization with device-to-device and cycle-to-cycle variations is performed on 28 nm bulk Si FeFET technology platform. The supporting TCAD simulations point towards the presence of an uneven number of FE/DE phases near Source-Channel vs Drain-Channel boundary to be the main cause of asymmetric current readout. Further, the simulation indicates that the novel non-destructive "capacitive" readout of a scaled FeFET to be more robust towards phase variation compared to the traditional current readout as the LPTS effect is amortized.

$\mathrm{HfO}_{\mathrm{x}}$-based ferroelectric (FE) field-effect transistor (FeFET) technology is a promising candidate for fast, low-power, low-cost, and high-density non-volatile memory and neuromorphic devices [1, 2]. However, charge trapping remains a key limiting factor, increasing the required read-after-write delay to $\sim \mathrm{ms}$ and limiting endurance. These effects are attributed to trapped electrons at the $\mathrm{SiO}_{2}-\mathrm{HfO}_{\mathrm{x}}$ interface or within $\mathrm{HfO}_{\mathrm{x}}[1,2]$. Previous studies investigated trapping through threshold voltage ($V_{\text {th }}$) memory window (MW) characterization [2, 3] and probed polarization charge $(P)$ by displacement current dynamics [4, 5]. In this work, we compare P, obtained from dynamic measurements, to the $\boldsymbol{V}_{\text {th }} \mathbf{M W}$ under varying de-trapping delay times and cycling conditions to gain deeper insight into the interplay between charge trapping, ferroelectric polarization, and the FeFET memory window.

Neuromorphic systems seek to replicate the functionalities of biological neural networks to attain significant improvements in performance and efficiency of AI computing platforms. However, these systems have generally remained limited to emulation of simple neurons and synapses; and ignored higher order functionalities enabled by other components of the brain like astrocytes and dendrites. In this work, drawing inspiration from biology, we introduce a compact Double-Gate Ferroelectric Field Effect Transistor (DG-FeFET) cell that can emulate the dynamics of both astrocytes and dendrites within neuromorphic architectures. We demonstrate that with a ferroelectric top gate for synaptic weight programming as in conventional synapses and a non-ferroelectric back gate, the DG-FeFET realizes a synapse with a dynamic gain modulation mechanism. This can be leveraged as an analog for a compact astrocyte-tripartite synapse, as well as enabling dendrite-like gain modulation operations. By employing a fully-depleted silicon-on-insulator (FDSOI) FeFET as our double-gate device, we validate the linear control of the synaptic weight via the back gate terminal (i.e., the gate underneath the buried oxide (BOX) layer) through comprehensive theoretical and experimental studies. We showcase the promise such a tripartite synaptic device holds for numerous important neuromorphic applications, including autonomous self-repair of faulty neuromorphic hardware mediated by astrocytic functionality. Coordinate transformations based on dragonfly prey-interception circuitry models are also demonstrated based on dendritic function emulation by the device. This work paves the way forward for developing truly "brain-like" neuromorphic hardware that go beyond the current dogma focusing only on neurons and synapses.