In this work, we present an experimental demonstration of a content addressable memory (CAM) cell based on ferroelectric HfO2 field effect transistors (FeFETs). Our proposed ferroelectric CAM (FeCAM) utilizes a CMOS-compatible ferroelectric material, hafnium zirconium oxide (HZO), as the gate dielectric. We discuss operation of the FeCAM cell and propose a suitable architecture to realize in-memory computation as well as single clock cycle content-driven search. In addition, the HZO FeFET is analyzed for its intrinsic memory characteristic, and design considerations are identified for improving device and therefore projected system-level performance. Our results indicate that FeCAM is well-suited to accommodate demanding modern computational needs by sealing the gaps between conventional memory, logic, and continued device scaling.

We report Negative Capacitance nFETs with a ~ 1 nm effective oxide thickness (EOT) gate stack. Experimental measurements show a clear steepening of the slope of the ID-VG characteristic in the weak inversion regime, indicating that a capacitance matching takes place there. This leads to non-linear behavior of the current in the log scale, which is not observed in conventional devices. Such steepening in the weak inversion regime leads to a significant increase in the achievable current at a constant VDD. At LG = 50 nm, our transistors show a larger than 2X increase in the ON current.

The ability to partially switch an FeFET could enable their use as an embedded low-voltage memory and as analog weight storage in artificial neural networks (ANNs). We report on memory characterization of FeFETs gated with 5.5-nm Hf 0.8 Zr 0.2 O 2 , fabricated on fully depleted silicon-on-insulator using a self-aligned, gate last process. We find that for a single device, excellent elevated temperature retention, program/erase endurance, and read endurance are obtained; however, there is significant device to device variability in the response of the ferroelectric to a partially switching program pulse, which may require the use of feedback in programming.

We investigate the impact of inner fringing fields on the negative capacitance FinFET (NC-FinFET) and how this scales with the technology node. The 8-/7-nm technology node of the p-type body NC-FinFET is modeled using the Sentaurus technology-aided design (TCAD), which couples Poisson with Landau equations. It is found that the NC effect is beneficial for device scaling. The OFF current is well suppressed in short-channel devices (64.4% reduction at L G = 16 nm) because the inner fringing field induces negative gate charges and decreases the channel potential. For longer channel devices, the influence of inner fringing field disappears, and the depletion charges dominate the subthreshold characteristics. As reducing remnant polarization, the ON current is boosted (11.4% improvement at L G = 16 nm) for all lengths due to better matching between MOSFET and ferroelectric capacitances. In comparison with FinFET, the drain-induced barrier lowering of NC-FinFET is also well controlled (50% reduction at L G = 16 nm) due to the inner fringing field-induced gate charges, showing the scaling capability of NC-FinFET. Furthermore, a compact model to capture the spatial distribution of the inner fringing field is also proposed based on the Gaussian quadrature method, and it is validated with the TCAD simulated data with multiple gate lengths and remnant polarizations.

We report on negative capacitance FETs (NCFETs) with a 1.8-nm-thick Zr-doped HfO 2 gate oxide layer fabricated on an FDSOI wafer. Hysteresis-free operation is demonstrated. When compared to a baseline that uses HfO 2 gate oxide with the same thickness, a subthreshold swing (SS) steeper by more than 20 mV/decade and larger than 10X reduction in the OFF current ( ${I}_{ \mathrm{OFF}}$ ) is observed at 30-nm channel length at constant ${I}_{ \mathrm{\scriptscriptstyle ON}}$ . On the other hand, at matched ${I} _{ \mathrm{\scriptscriptstyle OFF}}$ , the NCFET provides a larger ON current at constant ${V}_{\mathrm {DD}}$ . Our results indicate that the beneficial characteristic offered by the NCFETs can be obtained at scaled channel lengths, while using oxide layers whose thickness is comparable to the high- ${K}$ oxide layer used in ultra-scaled nodes.

A Monte Carlo TCAD simulation study of the impact of polycrystallinity and dielectric phases of the ferroelectric film on an 8/7 nm node NC-FinFET is presented. The study considers the random variation of ferroelectric remnant polarization $(\boldsymbol{P_{r}})$ and the presence of dielectric phases. In order to keep the ferroelectric-film induced device variability less than those induced by other sources (RDF, GER, FER, and MGG), we found that the DE content must be less than 20%, which is theoretically possible, and the grain to grain $\boldsymbol{P_{r}}$ variations less than 27%. While uniform single-crystalline ferroelectric film would provide the least device variation, we found 4 nm grains to produce less device variability than 5.3 nm grains due to the larger number of grains in the channel area.

We examine the nature of the interface states induced during the integration of ferroelectric hafnium zirconium oxide on silicon. Metal-ferroelectric-insulator-silicon capacitors, with a thin layer of hafnium zirconium oxide grown by atomic layer deposition as the ferroelectric and various interfacial oxide layers as the insulator, are investigated. Since a high-temperature post-annealing is necessary to induce the formation of the ferroelectric phase in this oxide stack, the integrity of the oxide/silicon interface must be preserved after high-temperature processing. As such, we show that a nitrided interlayer provides an improved midgap interface state density among all interfacial oxides investigated. Furthermore, we quantify the interface states using the ac conductance technique and model the interface trap distribution across the silicon bandgap in order to explain and verify the experimental measurements.

We report on the measurement of a 101-stage ring oscillator (RO) consisting of state-of-the-art 14 nm FinFET devices with a ferroelectric gate layer that exhibits negative capacitance. We show that the gate stage delay as a function of applied voltage can be directly modeled from DC characteristics of the individual NC-nFET and NC-pFET devices that constitute the RO, thereby demonstrating that there is no slowdown of the NC effect at the highest speed tested - per-stage delay as small as 7.2 ps.

Continuum phase-field simulations show how a multidomain ferroelectric capacitor in series with a resistor can exhibit a transient response in which the ferroelectric behaves as a negative capacitor. We show that accelerating domain growth leads to negative capacitance (NC), and this happens even when there is no initial switching of the domains. The observed behavior is in close agreement with experimental results of NC transients seen recently in a number of ferroelectric material systems.

Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

We report on negative capacitance (NC) FinFETs with ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (L CH ) of 450 nm to 30 nm and multiple fin widths (W FIN ) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), <60 mV/decade subthreshold swing (SS) with an average SS of 54.5 mV/dec for ~2 orders of I D and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same L ch /W Fin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.

A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. A 2D Numerical Simulation for FinFETs coupled with the Landau’s Ferroelectric Model captures device characteristics. A new version of the distributed Negative-Capacitance FinFET Compact Model is also presented in this work, where influence of short-channel effects in Ferroelectric voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, is presented for the gate voltage amplification of Negative Capacitance FinFETs in ring-oscillator circuits.

It is well known that one needs an external source of energy to provide voltage amplification. Because of this, conventional circuit elements such as resistors, inductors or capacitors cannot provide amplification all by themselves. Here, we demonstrate that a ferroelectric can cause a differential amplification without needing such an external energy source. As the ferroelectric switches from one polarization state to the other, a transfer of energy takes place from the ferroelectric to the dielectric, determined by the ratio of their capacitances, which, in turn, leads to the differential amplification. This amplification is very different in nature from conventional inductor-capacitor based circuits where an oscillatory amplification can be observed. The demonstration of differential voltage amplification from completely passive capacitor elements only, has fundamental ramifications for next generation electronics.

The emergence of negative capacitance as a way to limit power dissipation in CMOS logic transistors has raised the question of response delay of ferroelectric negative capacitance. Latency requirements for digital logic require a response time on the order of 10 ps or less. In this letter, we establish a coherent theoretical framework to analyze the delay between the clock edge at the gate and the response of the semiconductor channel in a ferroelectric negative capacitance transistor. The standard Landau-Khalatnikov equation approximates the slow, diffusive limit of the classical equation of motion. Therefore, using it to predict the response speed is unphysical. After extracting the damping and kinetic inductance from THz spectroscopy data, we simulate the full classical equation of motion and analyze the delay. We find that for doped hafnium oxides, the intrinsic delay is around 270 fs, far less than what is required for digital logic.

We have studied the effect of Zr doping, from 0% to 100%, on the ferroelectric properties of HfO 2 . Amorphous Hf x Zr 1-x O 2 on TiN and Si substrates is deposited using atomic layer deposition (ALD) and then annealed in a rapid thermal processing (RTP) tool while capped by 20 nm of sputtered TiN. Based on our experiments, Zr doping of up to 50% results in ferroelectricity in polycrystalline Hf x Zr 1-x O 2 , whereas Zr doping of 70% and above shows antiferroelectricity. Our results show how the properties of ferroelectric HfO 2 can be engineered through changing doping and annealing conditions, thereby demonstrating the flexibility of ferroelectric HfO 2 for integration in future memory and logic devices.

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf 0.8 Zr 0.2 O 2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 10 6 , a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 10 7 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

We present a simulation study of the negative capacitance effect incorporating leakage through the ferroelectric (FE) negative capacitor. The dynamics of the FE is modeled using the Landau-Khalatnikov equation. When an FE and a dielectric are simply connected in series without a metal contact between them, the stabilization of negative capacitance remains unchanged irrespective of leakage. However, when a metal is used, any finite leakage through the FE makes it impossible to stabilize negative capacitance at the steady state. Nonetheless, when a voltage is applied, the series configuration enters the negative capacitance state and as long as the gate voltage is cycled faster than the time needed by the leakage current to discharge all the capacitors, the transistor shows improved subthreshold swing. These results are expected to provide insight into understanding and analyzing recent experimental results on negative capacitance.