To investigate the effects of various pillar conditions such as pillar thickness (Tpillar), pillar height (TSi), and doping concentration of pillar on DC characteristics of TFETs with vertical structures (TFETVS) and AC switching characteristics of TFETVS inverters, Mixed-mode device and circuit TCAD simulations are performed. As 1) the Tpillar is thicker, 2) the TSi is increased, and 3) the doping concentration of the pillar is reduced, the tunneling current between source and channel gets increased and the gate-to-drain capacitance (CGD)-gate voltage (VG) curve becomes positive-shifted due to the weaker controllability of VG on the drain-side channel. Through the transient responses of TFETVS inverters with various pillar conditions, it is revealed that AC switching performance can be improved by the enhanced tunneling current and the positive-shifted CGD-VG curve caused by the weaker VG controllability on the drain-side channel.

Read disturbance is analyzed in vertically channel-stackedNAND flashmemory, which has string select transistors (SSTs) to access each channel layer independently. Additional read disturbance is observed at the cells adjacent to the selected cell in the unselected channel layers as well as typical read disturbance caused by repetitive Fowler-Nordheim tunneling (F-N) stress. Technology computer-aided design simulations and measurements are performed to investigate the disturbance mechanisms. It is found that bitline-side [common-source line-side] adjacent cell is disturbed by the hot carrier injection (HCI), which results from positively [negatively] boosted channel potential by the rising [falling] of the voltage (V-unsel) applied to unselected cells, respectively. A novel read operation, in which the selected cells aremaintained in turned on state during the V-unsel rising/falling and then are restored to their own states, is proposed to suppress the occurrence of the HCIs. As a result, it is revealed that the HCI-induced read disturbances are successfully suppressed by the proposed method.

In this paper, we propose a new type of nonvolatile memory (NVM) device based on a tunnel field-effect transistor (TFETs) with Ferroelectric HfO₂ sidewall. By simply utilizing the ferroelectricity of orthorhombic HfO₂ and conventional sidewall spacer technique, TFET can operate as a NVM device. The polarized charges in the ferroelectric HfO₂ spacer induced by program/erase pulse modulate the tunneling barrier between the source and channel; thus, change the threshold voltage (Vt) of TFET. The proposed NVM TFET has lower subthreshold swing (SS) and higher on/off ratio than conventional NVM TFETs while maintaining equivalent program/erase efficiency. Further-more, we also investigate the optimal HfO₂ sidewall formation conditions to achieve higher NVM performances.

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (<8 ns) and a large on-off current ratio (>107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

In order to verify the effects of polycrystalline Si (poly-Si) body thickness scale-down on read operation in 3D NAND flash memory which has tube type thin body, TCAD simulations and the measurements of fabricated devices are performed. I-D-V-G characteristics and transient drain current behaviors are investigated in 3D NAND devices with various body thicknesses and grain sizes. It has been known that drain current undershoot/overshoot is observed in poly-Si channel devices by falling/rising step gate bias. These phenomena are strongly related with transient of potential barrier height due to slow capture/emission rate of poly-Si grain boundary traps. As the body thickness decreases with the same grain size, the transient current instability, on-state current, and subthreshold-swing are improved. When the grain size is increased with the same body thickness, the transient current instability, on-state current, and subthreshold-swing are improved.

In this paper, novel boosting scheme using asymmetric pass voltage ( $\text{V}_{\mathrm{ pass}}$ ) is proposed to obtain high channel boosting potential and to reduce program disturbance in 3-D NAND flash memory. The proposed scheme has the same program bias and timing conditions as conventional self-boosting except for $\text{V}_{\mathrm{ pass}}$ voltages applied to both adjacent word-lines of selected word-line (WL sel ). Reduced $\text{V}_{\mathrm{ pass}}$ ( $\text{V}_{\mathrm{ pass1}} =\,\,\text{V}_{\mathrm{ pass}} - {\Delta }\text{V}$ ) is applied to previous word-line (WL $_{\rm n-{1}}$ ) of WL sel and increased $\text{V}_{\mathrm{ pass}}$ ( $\text{V}_{\mathrm{ pass2}} =\,\,\text{V}_{\mathrm{ pass}}+{\Delta }\text{V}$ ) is applied to next word-line (WL $_{\rm n+{1}}$ ). In this scheme, the $\text{V}_{\mathrm{ pass1}}$ cuts the channel off and causes local boosting when the channel potentials of inhibit strings are boosted up. Meanwhile, the $\text{V}_{\mathrm{ pass2}}$ compensates the program speed reduction of selected cell (cell sel ) induced by the decreased voltage of the $\text{V}_{\mathrm{ pass1}}$ . Through the measurements of program disturbance in fabricated devices, it is revealed that the program disturbance is significantly improved without the reduction of program speed by the proposed scheme. Furthermore, the $\text{V}_{\mathrm{ pass1}}$ and $\text{V}_{\mathrm{ pass2}}$ are optimized to maximize the improvement.

A novel fabrication method using a top SiO2-SiN-bottom SiO2 (ONO) dielectric stack is proposed and implemented to obtain ion sensitive field effect transistor (ISFET) with damage-free sensing oxide and threshold voltage (Vth)-tunable devices in CMOS read-out circuits. By wet-etching the top SiO2 and the SiN sequentially, the ISFET with damage-free sensing oxide is obtained due to the high selectivity between them. Also, the Vth-tunable circuit devices with the ONO stacks are simultaneously achieved by protecting the ONO stacks from the wet-etching. Through the measurements of pH and biomolecule responses, it is confirmed that the pH and biomolecule can be detected stably because the drain current (I-D) is stabilized to a predetermined value more quickly and the I-D fluctuation during the I-D stabilization is significantly reduced compared with devices having damaged sensing oxide. Additionally, it is verified that the Vth of devices for circuits can be fine-controlled by injecting charges into the SiN via Fowler-Nordheim tunneling. Furthermore, it is demonstrated that the biomolecule-induced Vth shift of similar to 150 mV in the proposed ISFET is successfully amplified to the output voltage change of similar to 370 mV in common source amplifier (CSA) voltage-readout circuit consisting of one p-type ISFET and one Vth-tuned n-type MOS. (C) 2018 Elsevier B.V. All rights reserved.

Numerous researches for making steep tunnel junction within tunnel field-effect transistor (TFET) have been conducted. One of the ways to make an abrupt junction is source/drain silicidation, which uses the phenomenon often called silicide-induced-dopant-segregation. It is revealed that the silicide process not only helps dopants to pile up adjacent to the metal-silicon alloy, also induces the dopant activation, thereby making it possible to avoid additional high temperature process. In this report, the availability of dopant activation induced by metal silicide process was thoroughly investigated by diode measurement and device simulation. Metal-silicon (MS) diodes having p+ and n+ silicon formed on the p- substrate exhibit the characteristics of ohmic and pn diodes respectively, for both the samples with and without high temperature annealing. The device simulation for TFETs with dopant-segregated source was also conducted, which verified enhanced DC performance.

A complete simulation framework is presented for Negative Capacitance FinFETs including Numerical Simulation, Compact Modeling, and Circuit Evaluation. A 2D Numerical Simulation for FinFETs coupled with the Landau’s Ferroelectric Model captures device characteristics. A new version of the distributed Negative-Capacitance FinFET Compact Model is also presented in this work, where influence of short-channel effects in Ferroelectric voltage amplification are newly incorporated. Finally, a detailed analysis, from an energy perspective, is presented for the gate voltage amplification of Negative Capacitance FinFETs in ring-oscillator circuits.

In this study, we investigated the effects of nanowire size on the current sensitivity of silicon nanowire (SiNW) ion-sensitive field-effect transistors (ISFETs). The changes in on-current (Ion) and resistance according to pH were measured in fabricated SiNW ISFETs of various lengths and widths. As a result, it was revealed that the sensitivity expressed as relative Ion change improves as the width decreases. Through technology computer-aided design (TCAD) simulation analysis, the width dependence on the relative Ion change can be explained by the observation that the target molecules located at the edge region along the channel width have a stronger effect on the sensitivity as the SiNW width is reduced. Additionally, the length dependence on the sensitivity can be understood in terms of the resistance ratio of the fixed parasitic resistance, including source/drain resistance, to the varying channel resistance as a function of channel length.

A novel fabrication process is proposed to form an ion-sensitive field effect transistor (ISFET) with damage-free gate oxide and a threshold voltage (VT)-tunable complementary metal-oxide semiconductor (CMOS) readout circuit with oxide-nitride-oxide (ONO) stacked gate dielectric simultaneously. In the ISFET, high-quality sensing oxide can be obtained by adopting a three-step sensing-area etch process that uses silicon nitride as an etch stopper. Furthermore, the VT value of the CMOS can be tuned appropriately by storing electrons or holes in the silicon nitride of the ONO gate stack through Fowler Nordheim (FN) tunneling. By using a mixed-mode device and circuit simulations, the ability of minute VT tuning is verified in the ONO-stacked CMOS. Moreover, the influence of VT tuning on the sensitivity is investigated in a common source amplifier (CSA) readout circuit consisting of the ISFET and a MOSFET with the ONO gate stack.

In order to verify the effects of large gate-to-drain capacitance (C-gd) coupled with low tunneling current on the switching characteristics of tunnel field-effect transistor (TFET) inverters, TFET and MOSFET inverter circuits with equalized saturation current (I-sat) and C-gd levels are simulated with the help of mixed-mode device and circuit simulations. From the simulation results, it is revealed that additional mechanisms also degrade the pre-shoot and falling/rising delay of the output voltage (V-out) as well as the low tunneling current and large C-gd inherent in TFETs. A one-directional current flow due to the asymmetric polarity of the source/drain and the superlinear onset of the output characteristics along with an ambipolar current are found to be among the main causes of the pre-shoot and the falling/rising delay, respectively.

In this paper, we investigate the polysilicon grain boundary (GB) trap with extremely thin floating body MOSFET. When the electron-hole pair is generated by impact ionization mechanism, excess holes migrate toward the GB and are trapped by it. This phenomenon can modify energy band structure, and cause floating body effect although the body is fully depleted. That means ultrathin polysilicon channel device has a possibility as a capacitor-less DRAM operation. The TCAD simulation and measurement data represents that the drain current reverts to its previous level over 80 mu sec after drain pulse, and this can be utilized as memory mechanism.

A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias (V G )/positive drain bias (V D ) in amorphous hafnium-indium-zinc-oxide thin-film transistors. Negative threshold voltage (V th ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of (V G = -5V, V D = 15V,and V =0V) and (V G = -5 V, V D = 0 V, and V = 15 V) under light illumination, it is found that the negative V th shift is affected only by V G , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by V D induced drain-side trapped holes. Furthermore, the drain side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance (C GD ) was measured before/after the (V G = -5 V, V D = 15 V, and V = 0 V) stress to clarify the presence and distribution of the drain-side trapped holes. From CG D stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress.

In this letter, we propose the use of tunneling field effect transistors (TFET) as a biosensor that detects bio-molecules on the gate oxide. In TFET sensors, the charges of target molecules accumulated at the surface of the gate oxide bend the energy band of p-i-n structure and thus tunneling current varies with the band bending. Sensing parameters of TFET sensors such as threshold voltage (Vt) shift and on-current (ID) change are extracted as a function of the charge variation. As a result, it is found that the performances of TFET sensors can surpass those of conventional FET (cFET) based sensors in terms of sensitivity. Furthermore, it is verified that the simultaneous sensing of two different target molecules in a TFET sensor can be performed by using the ambipolar behavior of TFET sensors. Consequently, it is revealed that two different molecules can be sensed simultaneously in a read-out circuit since the multi-sensing is carried out at equivalent current level by the ambipolar behavior.

The temperature dependence of MOSFET and TFET-based pH sensitive ISFET was investigated through TCAD device simulation. The transfer characteristics and the pH sensitivities of both devices at various temperature were compared. TFET-based ISFET exhibits superior thermal stability in contrast with the MOSFET-based ISFET due to the difference of conduction mechanism.

Tunnel field-effect transistor (TFET) with asymmetric gate dielectric and body thickness (TFETAsy) is proposed. The TFETAsy not only reduces the tunneling resistance by using the thinner source-side gate dielectric and body, but also suppresses the ambipolar current (Iambipolar) and the degradation of alternating current (AC) switching performances with the thicker drain-side gate dielectric and body. Technology computer aided design process and device/circuit simulations are performed to verify the validity of the TFETAsy in terms of fabrication process and electrical characteristics. From the simulation results, it is revealed that the thinner source-side gate dielectric and body can be simply formed by oxide wet-etching after the selective oxidation of the source-side body. Moreover, the thinner source-side SiGe body can be also formed by using Ge condensation process instead of the oxidation. Additionally, it is confirmed that the TFETAsy has higher on-current, steeper subthreshold swing, lower Iambipolar and improved AC switching characteristics as compared to those of conventional TFET with symmetric structure.

A new type of ISFET is proposed where the proposed ISFET channel is divided into a gate controlled region (Region(gate)) and sensing region (Region(sense)). The ISFET is operated by controlling the gate voltage of the Regiongate with the attached biomolecules on the gate dielectric of the Regionsense. When the gate voltage is applied over the threshold voltage (14n), the channel resistance of the Regiongote sharply decreases and the larger channel resistance of the Regionsense limits the ISFET current. Thus, the on-current (I-on) of the ISFET is controlled by the attached biomolecule charge on the gate dielectric of the Region(sense). Our proposed ISFET has many advantages over conventional ISFETs. From TCAD simulations, the proposed ISFET was found to have higher sensitivity according to pH levels than conventional ISFETs due to the unique limitation of the I-on by the channel resistance change of the Region(sense). Additionally, the field-dependent drift effect can be mitigated, because hydrogen ions or biomolecules in the solution are hardly affected by the gate voltage. Furthermore, the proposed ISFET has uniform Ion change regardless of Vth variation, because only the channel resistance of the Regionse, determines the I-on.

In terms of the application of the ion sensitive field effect transistor (ISFET) fabricated with top-down approached and CMOS-compatible back-end process to integrated circuits, the macro model of the ISFET is required. Although several models have been reported, there is no electrical model that reflects the time-dependent drain current (I-D) change (drift effect). We propose the electrical model which can reflect the drift effect and can be expressed by the combination of electrical circuit components. In the proposed model, R-1 represents the resistance of the electrolyte and the FET can be approximated by the capacitances C-1 (capacitance of pure gate oxide in which hydrogen ions move very slowly) and C-2 (capacitance by gate oxide with defects in which hydrogen ions move relatively faster). Furthermore, the movement of hydrogen ions in the defective oxide is represented by R-2 and the current drift is modeled as the parallel combination of the C-2 and the R-2 because the drift effect is strongly related to hydrogen ion movement through defective gate oxide or Helmholtz layer. Consequently, the ISFET with the I-D drift can be modeled by the series connection of the RI, the parallel combination of the C-2 and the R-2, and the C-1. Also, The ID calculated by the proposed model is successfully fitted to the measured time-dependent ID of the ISFET. (C) 2017 Elsevier B.V. All rights reserved.