Resistive memory is a promising alternative to SRAM, but is also an inherently unstable device that requires substantial effort to ensure correct read and write operations. To avoid the associated costs in terms of area, time and energy, the present work is concerned with exploring how much noise in memory operations can be tolerated by image classification tasks based on neural networks. We introduce a special noisy operator that mimics the noise in an exemplary resistive memory unit, explore the resilience of convolutional neural networks on the CIFAR-10 classification task, and discuss a couple of countermeasures to improve this resilience.

In this work, the effect of ultrathin Al2O3 insertion layer on the endurance characteristics of Hf0.5Zr0.5O2 (HZO) layer is statistically investigated. It was found that the ultrathin Al2O3 insertion layer will not improve or reduce the endurance of HZO devices within the low operation voltage range. However, an abrupt endurance degradation phenomenon is observed when increasing the operation voltage to a specific value and the endurance of Hf0.5Zr0.5O2 layer is sharply lower than HZO device. This phenomenon is finally explained by the leakage-current-assist polarization switching mechanism after quantitatively extracting the continuous charge density during the polarization switching by pulse measurement. The findings of this work provide a deep understanding of the endurance failure mechanism of Ferroelectric/Dielectric (FE/DE) devices and are helpful for the reliability investigation of the gate stack in Fe-FET.

The 3-D nand technology has garnered increasing attention within space applications as a focal point of commercial competition and industrial evolution in semiconductor memory. With the increase in the number of layers, dual-deck architecture is being gradually integrated into products to reduce process fluctuations and improve electrical performance. However, it is essential to carefully evaluate the response of such new devices to radiation effects. In this study, the 3-D distribution characteristics of single-event upsets (SEUs) were investigated in 128-layer dual-deck 3-D nand flash memory induced by heavy ion irradiation. By measuring the threshold voltage distribution of charge-trapping (CT) cells under different heavy ion conditions, the dependence of the number and size of multiple cell upsets (MCUs) on the linear energy transfer (LET) was analyzed, and the underlying physical mechanisms of these radiation effects were explored. In addition, the variation of SEU along the layer is closely related to the dual-deck structure and channel hole etch process. This work provides important reference data for improving the reliability design of 3-D nand flash devices in radiation environments.

Heavy ion irradiation effects on charge trapping memory (CTM) capacitors with TiN/Al2O3/HfO2/Al2O3/HfO2/SiO2/p-Si structure have been investigated. The ion-induced interface charges and oxide trap charges were calculated and analyzed by capacitance–voltage (C–V) characteristics. The C–V curves shift towards the negative direction after swift heavy ion irradiation, due to the net positive charges accumulating in the trapping layer. The memory window decreases with the increase of ion fluence at high voltage, which results from heavy ion-induced structural damage in the blocking layer. The mechanism of heavy ion irradiation effects on CTM capacitors is discussed in detail with energy band diagrams. The results may help to better understand the physical mechanism of heavy ion-induced degradation of CTM capacitors.

Based on the BL09 terminal of China Spallation Neutron Source (CSNS), single event upset (SEU) cross sections of 14 nm fin field-effect transistor (FinFET) and 65 nm quad data rate (QDR) static random-access memories (SRAMs) are obtained under different incident directions of neutrons: front, back and side. It is found that, for both technology nodes, the “worst direction” corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume. The SEU cross section under the worst direction is 1.7–4.7 times higher than those under other incident directions. While for multiple-cell upset (MCU) sensitivity, side incidence is the worst direction, with the highest MCU ratio. The largest MCU for the 14 nm FinFET SRAM involves 8 bits. Monte–Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

In this study, the TID effects on the FTJs with HfO2/Al2O3 dielectric bilayer are investigated. The P-V, C-V, I-V, endurance, and read current characteristics are analyzed before and after radiation. The I-V, P-V and endurance characteristics show very little change after the total dose of up to 1 Mrad (Si), which means the ferro-electricity is not affected by the TID. However, owing to the positive fixed charges formed in Al2O3 film and the interface traps accumulation during the radiation, the read current of the programed device is increasing, while the read current of the erased device is reducing after radiation. These findings are useful in understanding the radiation mechanisms of HfO2/dielectric bilayer-based FTJs and can promote the application of FTJs in the nuclear and aerospace environments.

开展了 60Coγ射线辐照柔性基底石墨烯霍尔传感器的总剂量效应实验研究,测量并分析了在γ射线辐照至1 Mrad前后柔性基底石墨烯霍尔传感器的电学性能.γ射线辐照后,传感器的霍尔电压、线性度、失调电压和电流相关灵敏度均略有降低,电流相关灵敏度下降了约8％.主要原因是辐照后传感器中引入了少量的杂质和缺陷,导致器件的均一性和对称性略有变化.分析了电离辐射与柔性基底石墨烯的霍尔传感器的相互作用,可为该种类传感器在空间或其他辐射敏感环境中的应用提供数据基础.

Single-bit upset (SBU) and multiple-cell upset (MCU) features of high-speed QDR-SRAM are revealed under the 14 MeV neutron irradiation. By comparing with the high-altitude real atmosphere test results directly, the equivalence of 14 MeV neutrons for atmospheric neutron-induced single event effect (SEE) evaluation is investigated. It is found that, compared with the 65 nm planar device, the SBU cross-section of 14 nm FinFET SRAM decreases to 1/58 and the proportion of MCU shows little difference, which results from the narrow channel between fin and substrate caused by shallow channel isolation in 14 nm FinFET process, and the charge sharing effect between fins is weakened. The SBU and MCU cross-sections under the 14 MeV neutron irradiation are underestimated by 22.8% and 85.7%, respectively. Besides, the probability and maximum size of MCU are both smaller than those in the real atmosphere. The MCU shape tends to be vertical, resulting from the smaller vertical spacing of sensitive volumes (about 100 nm). Further Monte-Carlo simulation shows that the total yield of secondary ions produced by atmospheric neutrons is higher than that produced by 14 MeV neutrons. Major Components of the “useful” products are p, Si, α, etc., which are the main cause of SBU events. Besides, compared with 14 MeV neutrons, atmospheric neutrons generate more kinds of secondary ions in the SV within the scope from p to W, and the diverse high-Z elements, such as W, Ta, Hf, etc., are the main cause of MCU events. Moreover, the maximum LET of secondary ions can reach 31.5 MeV·cm2/mg. The equivalence of using 14 MeV neutrons for atmospheric neutron-induced SEE evaluation is closely related to the critical charge of the device under test.

In this work, we proposed a digital flash computing-in-memory (CIM) architecture using compressed lookup-table multiplier (CLUTM) and low power word-line voltage trimming (LP-WLVT) schemes. The proposed concept is highly compatible to the standard commodity NOR flash memory. Compared to the conventional lookup-table (LUT) multipliers, CLUTM results in 32 times reduction on the area cost in the case of 8-bit multiplication. The LP-WLVT scheme can further reduce the inference power by 14%. The concept is silicon demonstrated in a 55nm 32Mb commercial flash memory, which can perform 8-bit multiply-and-accumulate (MAC) with a throughput of 51.2 GOPs. It provides 1.778ms frame shift when running TC-resnet8 network, which is $5 \times$ more efficient than the previous works. The CLUTM-based digital CIM architecture can play an important role to enable commercial flash for highly-efficient AI edge inference.

In order to meet the requirements of an Internet of Things (IoT) application with high capacity data storage, a 64M bit resistive random access memory (RRAM) has been designed and fabricated successfully using 180 nm Silterra technology. In the design, the memory cell adopts the one-transistor-one-resistor (1T1R) structure and the layout of the memory cell is optimized to minimize the chip area. In order to maximize the performance of the RRAM, the method of split array and hierarchical decoding are adopted in the circuit design. To ensure the correct readout of data, 32 reference word lines can be connected with different reference resistors to generate appropriate reference current while the sense amplifier (SA) circuit is specially designed to achieve fast data readout. Using this circuit we achieved a measurement result for the 64M bit RRAM chip, the read access time is less than 20 ns, the data retention time is more than 10 years, and the endurance is more than 107 cycles.

This paper presents a low-latency BCH-CRC decoder for 3D CT NAND flash memory. The presented decoder uses the hard-decision values as the input, which can avoid the energy-consuming sensing operations for generating the soft-decision values and hence extend the life time of flash memory. In order to improve the error correction performance, a BCH-CRC concatenated coding scheme is developed. Moreover, the BCH decoding algorithm is optimized to reduce the overall cost of the decoder. We implement the proposed decoder targeting at 3D CT NAND flash memory applications. The user data length is 512 bytes, which is divided into four segments. A 16-bit CRC is appended to each segment, and then the message sequence is encoded by a BCH code with 9-bit error correction capacity. The decoder is realized in a 65nm CMOS process, which can achieve a decoding throughput of 191MB/s with latency 2.795µs.

To understand the possible potentials of large capacity NAND flash memory chips in harsh environment applications, in this work, the impacts of total ionizing dose (TID) in charge-trap (CT) 3D NAND are characterized experimentally. Typical floating-gate (FG) 2D NAND chips are also tested for comparisons. Different from its FG 2D counterpart, error bits in raw CT 3D NAND flash memory has ignorable degradations in the same dose of ionizing radiation. However, high dose ionizing radiation still cause 3D NAND chip failure, the recovery of the failed chip after annealing at room temperature was also recorded, the underlying. Our results are important for future development of CT flash memories aiming at robust reliabilities.

A novel vertical tunnelling field-effect transistor (TFET) based on silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory device, named as VT-SONOS, is proposed and investigated using TCAD simulations. Different from traditional planar TFET-based SONOS memory, the VT-SONOS device is programmed via band-to-band tunnelling for vertical pocket and Fowler–Nordheim tunnelling for both pocket/bottom oxide (OXb) and channel/OXb regions, which leads to a steeper subthreshold swing (SS) and a larger on-state current (I ON). The device structure is constructed using Sentaurus TCAD tools, and I D–V G characteristics were extracted using TCAD tools. Obtained SS value is 102.09 mV dec−1, while the I ON was 3.02 × 10−4 A. The memory window was 2.95 V, showing more dependence on programming pulse height (V gp) than erasing pulse height (V ge). Furthermore, 10-year retention characteristics were studied to investigate critical reliability issue. About 60% of the initial trapped charges remained in the device after unbiased 3.15 × 108 s (10 years) storage.

In this letter, sub-10-nm air channel devices were fabricated with the aid of photolithography and focused ion beam (FIB) etching. Field emission ( FE) properties of the device weremeasured under ambient conditions. The operation mechanism was discussed by means of current-voltage (I-V) curve fitting and energy band diagram analysis. On account of the extremely shrinking of nanogap, record-high emission currents of 355.6 mu A at 1 V were realized in air with a threshold voltage as low as 0.588 V. A cycle test of 200 times was also performed to verify and analyze the stability of the device. Importantly, the temporal response performance of the device was also measured. It demonstrated a high-speed and repeatable output waveform with a rise/fall time of similar to 100 ns. This study demonstrates a practical nano-fabrication technology to fabricate sub-10-nm air channel devices with ultra-low operating voltage, which can be utilized as an electrical element in high-speed and low-power integrated circuits.

The single event effects (SEEs) on ferroelectric Hf 0.5 Zr 0.5 O 2 capacitor-based non-volatile static random access memory (nvSRAM) were investigated by simulation. A nvSRAM cell integrated with two ferroelectric Hf 0.5 Zr 0.5 O 2 capacitors is proposed in this study. A macro-model of the ferroelectric Hf 0.5 Zr 0.5 O 2 capacitor, extracted from the real fabricated devices, is utilized for simulation analysis. Fundamental store and recall operations of the proposed nvSRAM design have been demonstrated. An independent double exponential current source was utilized and injected into specific circuit nodes to simulate the heavy ion induced single event transient current. The simulation results show that the transient pulse current is possible to upset the logic state of the memory cell from 1 to 0, but whether it can recover in a short time period after the upset errors depends on the exact value of linear energy transfer for the injected particles. In addition, increasing the remnant polarization ( P r ) and decreasing the coercive voltage ( V c ) and film thickness of ferroelectric capacitors can mitigate the influence of SEEs, which provides guidance for process hardening techniques aiming at space applications.

In this work, the study of the single event effects (SEEs) in capacitor-less one-transistor dynamic random access memory (1T-DRAM) based on an indium gallium arsenide on insulator (InGaAs-OI) transistor is conducted for the first time. The electrical properties of the 90-nm device are numerically simulated to determine appropriate operation condition. The successful memory behaviors are observed due to the gate-induced drain leakage (GIDL) programming method. The impacts of different linear energy transfer (LET) values, high-energy particle (HEP) strike positions and directions, and HEP hitting moments on the memory performance are investigated via simulations. Unlike the conventional SOI device, the source and drain in 1T-DRAM cells are found to be sensitive to SEEs with a higher transient current. The single event upsets (SEUs) are found to occur only when the HEP hits the device at reading “0” state and holding state before read “0.” An increased read-out current is obtained after the HEP strike due to the GIDL- and SEE-induced accumulative floating holes. The related mechanisms are discussed in detail. These results and discussions are useful for the development of the SEE hardening of 1T-DRAM-based embedded memory for space applications in the future.

The effects of proton radiation on TiN/Zr-doped-HfO2(HZO)/Al2O3/P+-Ge ferroelectric tunneling junctions are investigated in the present work. The electrical characteristics are measured before and after different proton fluences. The remanent polarization exhibits negligible change, which demonstrates the proton radiation immunity of the ferroelectric material HZO. However, the capacitance, leakage current, endurance, and read current characteristics show obviously changed with the increase of proton fluence. The main reason for this is that proton radiation causes positive fixed charges to form in the Al2O3 layer, interface charges to form in Al2O3/Ge and the effective carrier concentration to reduce in the Ge substrate.

The effects of total dose irradiation on graphene-based Hall sensors were investigated by Co-60 gamma-ray in this paper. The basic electrical parameters of the sensors were measured before and after gamma-ray irradiation up to 1 Mrad(Si). Decreases in the Hall voltage, linearity and current-related sensitivity in response to gamma-ray irradiation were observed. With the help of Raman spectroscopy and X-ray photoelectron spectra (XPS), the degradation after irradiation was attributed to the introduction of defects and the increase in doping concentrations in the graphene layer. Moreover, the introduction of defects and impurities enhanced the Coulomb scattering of carriers, resulting in a decrease in mobility, which in turn affected the sheet resistance. This work provides an insight into the interactions of ionizing irradiation with graphene-based Hall sensors, which could be applied in space or other irradiation sensitive applications.

In this paper, a radiation-hardened resistive random-access memory (RRAM)-based non-volatile (NV) latch with a dual-interlocked storage cell is proposed and analyzed. The single-event effects of the proposed NV latch are simulated and discussed. Simulations of the proposed element are based on a 0.18 mu m complementary metal-oxide-semiconductor design kit for the peripheral circuit and the voltage threshold adaptive memristor model for the RRAM. The simulation results indicate that the injected charge to induce a single-event upset (SEU) of the proposed NV latch is above 4.5 pC. As compared to the traditional RRAM based NV latch, the proposed NV latch is relatively immune to an SEU. This immunity from the SEU originates from the redundant storage nodes and interlocked feedback mechanism. Moreover, the area overhead of the proposed NV latch (eight transistors in the core storage element) are much lower than other radiation-hardened technology, e.g. TMR or FERST.

Based on the wide-spectrum neutron beam (covering thermal neutrons and E > 10 MeV neutrons, with maximum energy of 1.6 GeV) provided by the China Spallation Neutron Source (CSNS), this paper focuses on the single event effect study of 14 nm FinFET large-capacity SRAM and 65 nm planar process SRAM device, using combined techniques of irradiation experiment, reverse analysis, and Monte-Carlo neutron transport simulation. The aim is to reveal the effect of integrated circuit process changing on the sensitivity of neutron induced single-bit and multiple-bit upsets (MBU), and to analyze the inner mechanisms, including the distribution of secondary particles in the sensitive volume, the characteristics of deposited charges, etc. The results show that compared with the 65 nm device, single event upset (SEU) cross section of the 14 nm FinFET device, induced by E > 10 MeV neutrons, is reduced by about 40 times, while the MBU ratio increases from 2.2% to 7.6%, which is due to the reduction of sensitive volume size of the 14 nm FinFET device (80 nm × 30 nm × 45 nm), pitch, and critical charge (0.05 fC). The main forms of MBU are double-bit upset, triple-bit upset and quadruple-bit upset. Unlike the phenomenon that the 65 nm device is immune to thermal neutrons, the use of the 10B element near M0 in the 14 nm FinFET device causes it to present the thermal neutron sensitivity to a certain extent. The SEU cross section induced by thermal neutrons is about 4.8 times smaller than that induced by E > 10 MeV neutrons. Based on the device cross-section and memory area images obtained from the reverse analysis, a device model is established and neutron transport simulation based on Geant4 toolkit is carried out. The E > 10 MeV neutrons result in abundant secondary particle distribution in the sensitive volume of the device, covering n, p into even W. The neutron energy and presence or absence of the W plug near the sensitive volume have an importantinfluence on the type and probability of secondary particles in the sensitive volume. The analysis and calculations show that a large number of high-Z secondary particles with long range and large LET values generated by high-energy neutrons in the sensitive volume of the device are the inducement of MBU, and SEUs mainly result from the contribution of light ions such as p, He, and Si.