Uncertainty estimation in Neural Networks (NNs) is vital in improving reliability and confidence in predictions, particularly in safety-critical applications. Bayesian Neural Networks (BayNNs) with Dropout as an approximation offer a systematic approach to quantifying uncertainty, but they inherently suffer from high hardware overhead in terms of power, memory, and computation. Thus, the applicability of BayNNs to edge devices with limited resources or to high-performance applications is challenging. Some of the inherent costs of BayNNs can be reduced by accelerating them in hardware on a Computation-In-Memory (CIM) architecture with spintronic memories and binarizing their parameters. However, numerous stochastic units are required to implement conventional dropout-based BayNN. In this paper, we propose the Scale Dropout, a novel regularization technique for Binary Neural Networks (BNNs), and Monte Carlo-Scale Dropout (MC-Scale Dropout)-based BayNNs for efficient uncertainty estimation. Our approach requires only one stochastic unit for the entire model, irrespective of the model size, leading to a highly scalable Bayesian NN. Furthermore, we introduce a novel Spintronic memory-based CIM architecture for the proposed BayNN that achieves more than $100\times$ energy savings compared to the state-of-the-art. We validated our method to show up to a $1\%$ improvement in predictive performance and superior uncertainty estimates compared to related works.

Neural Networks (NNs) provide an effective solution in numerous application domains, including autonomous driving and medical applications. Nevertheless, NN predictions can be incorrect if the input sample is outside of the training distribution or contaminated by noise. Consequently, quantifying the uncertainty of the NN prediction allows the system to make more insightful decisions by avoiding blind predictions. Therefore, uncertainty quantification is crucial for a variety of applications, including safety-critical applications. Bayesian NN (BayNN) using Dropout-based approximation provides a systematic approach for estimating the uncertainty of predictions. Despite such merit, BayNNs are not suitable for implementation in an embedded device or able to meet high-performance demands for certain applications. Computation in-memory (CiM) architecture with emerging non-volatile memories (NVMs) is a great candidate for high-performance and low-power acceleration BayNNs in hardware. Among NVMs, Magnetic Tunnel Junction (MTJ) offer many benefits, but they also suffer from various non-idealities and limited bit-level resolution. As a result, binarizing BayNNs is an attractive option that can directly implement BayNN into a CiM architecture and able to achieve benefits of both CiM architecture and BayNNs at the same time. Conventional in-memory hardware implementations emphasize conventional NNs, which can only make predictions, and do not account for both device and input uncertainty, thus, reducing both reliability and performance. In this paper, we propose for the first time Binary Bayesian NNs (BinBayNN) with an end-to-end approach (from algorithmic level to device level) for their implementation. Our approach takes the inherent stochastic properties of MTJs as a feature to implement Dropout-based Bayesian Neural Networks. We provide an extensive evaluation of our approach from the device level up to the algorithmic level on various benchmark datasets.

Bayesian Neural Networks (BayNNs) can inherently estimate predictive uncertainty, facilitating informed decision-making. Dropout-based BayNNs are increasingly implemented in Spintronics-based computation-in-memory architectures for resource-constrained yet high-performance safety-critical applications. Although uncertainty estimation is important, the reliability of Dropout generation and BayNN computation is equally important for target applications but is overlooked in existing works. However, testing BayNNs is significantly more challenging compared to conventional NNs, due to their stochastic nature. In this paper, we present for the first time the model of the non-idealities of the Spintronics-based Dropout module and analyze their impact on uncertainty estimates and accuracy. Furthermore, we propose a testing framework based on repeatability ranking for Dropout-based BayNN with up to 100% fault coverage while using only 0.2% of training data as test vectors.

Bayesian Neural Networks (BayNNs) are powerful tools for making predictions while also providing uncertainty estimates, a crucial aspect in safety-critical systems. However, implementing BayNNs in edge applications poses challenges, often necessitating transformations such as quantification or approximation, especially for Gaussian processes, commonly achieved through Dropout methods. This paper explores a new implementation of the Dropout module by using Superparamagnetic Tunnel Junction (SMTJ). The stochastic circuit enables fine-tuning of the generated stochastic bitstreams used to drop different parameters in the BayNN. The proposed module implementation leads to better power efficiency and robustness against variability. The results demonstrate an improvement in the energy efficiency of up to 34.8x when compared to the related works.

Internet of Things (IoT) and smart wearable devices for personalized healthcare will require storing and computing ever-increasing amounts of data. The key requirements for these devices are ultra-low-power, high-processing capabilities, autonomy at low cost, as well as reliability and accuracy to enable Green AI at the edge. Artificial Intelligence (AI) models, especially Bayesian Neural Networks (BayNNs) are resource-intensive and face challenges with traditional computing architectures due to the memory wall problem. Computing-in-Memory (CIM) with emerging resistive memories offers a solution by combining memory blocks and computing units for higher efficiency and lower power consumption. However, implementing BayNNs on CIM hardware, particularly with spintronic technologies, presents technical challenges due to variability and manufacturing defects. The NeuSPIN project aims to address these challenges through full-stack hardware and software co-design, developing novel algorithmic and circuit design approaches to enhance the performance, energy-efficiency and robustness of BayNNs on sprintronic-based CIM platforms.

Bayesian Neural Networks (BayNNs) naturally provide uncertainty in their predictions, making them a suitable choice in safety-critical applications. Additionally, their realization using memristor-based in-memory computing (IMC) architectures enables them for resource-constrained edge applications. In addition to predictive uncertainty, however, the ability to be inherently robust to noise in computation is also essential to ensure functional safety. In particular, memristor-based IMCs are susceptible to various sources of non-idealities such as manufacturing and runtime variations, drift, and failure, which can significantly reduce inference accuracy. In this paper, we propose a method to inherently enhance the robustness and inference accuracy of BayNNs deployed in IMC architectures. To achieve this, we introduce a novel normalization layer combined with stochastic affine transformations. Empirical results in various benchmark datasets show a graceful degradation in inference accuracy, with an improvement of up to $58.11\%$.

Typical neural networks are incapable of effectively estimating prediction uncertainty, leading to overconfident predictions. Estimating uncertainty is crucial for safety-critical tasks such as autonomous vehicle driving and medical diagnosis and treatment. Bayesian Neural Networks (BayNNs), which combine the capabilities of neural networks and Bayesian inference, are an effective approach for uncertainty estimation. However, BayNNs are computationally demanding and necessitate substantial memory resources. Computation-in-memory (CiM) architectures uti-lizing emerging resistive non-volatile memories such as Spin- Orbit Torque (SOT) have been proposed to increase the resource efficiency of traditional neural networks. However, training scalable and efficient BayNNs and implementing them in the CiM architecture presents its own challenges. In this paper, we propose a scalable Bayesian NN framework via Subset-Parameter inference and its Spintronic-based CiM implementation. Our method is evaluated on large datasets and topologies to show that it can achieve comparable accuracy while still being able to estimate uncertainty efficiently at up to 70 × lower power consumption and 158.7× lower storage memory requirements.

The deployment of Edge AI requires energy-efficient hardware with a minimal memory footprint to achieve optimal performance.One approach to meet this challenge is the use of Binary Neural Networks (BNNs) based on non-volatile in-memory computing (IMC).In recent years, elegant ReRAMbased IMC solutions for BNNs have been developed, but they do not extend to the first layer of a BNN, which typically requires non-binary activations.In this paper, we propose a modified first layer architecture for BNNs that uses k-bit input images broken down into k binary input images with associated fully binary convolution layers and an accumulation layer with fixed weights of {$2^{-1},...,2^{-k}$}.To further increase energy efficiency, we also propose reducing the number of operations by truncating 8-bit RGB pixel code to the 4 most significant bits (MSB).Our proposed architecture only reduces network accuracy by 0.28\% on the CIFAR-10 task compared to a BNN baseline.Additionally, we propose a cost-effective solution to implement the weighted accumulation using successive charge sharing operations on an existing ReRAM-based IMC solution.This solution is validated through functional electrical simulations.

The efficiency of known algorithms for solving NP- hard problems is constrained by the limitations of conventional von Neumann architectures. Recurrent networks of stochastic neurons are an appealing alternative to conventional computing architectures, as they potentially allow exploring the binary search space of NP-hard problems with limited resources and overheads. In this study, we consider the case of Boolean Satisfiability on small logic functions, with technological implementations based on Spin-Orbit Torque Magnetic Tunnel Junctions. We propose innovative circuit-level implementations of invertible logic architectures for an AND gate and a Full Adder, emphasizing the design constraints of such invertible logic operations. Simulation results demonstrate the feasibility of SOT-based implementations, and their robustness against process variations. The realistic implementation enables identifying the main power efficiency trade-offs.

Recent development in neural networks (NNs) has led to their widespread use in critical and automated decision-making systems, where uncertainty estimation is essential for trustworthiness. Although conventional NNs can solve many problems accurately, they do not capture the uncertainty of the data or the model during optimization. In contrast, Bayesian neural networks (BNNs), which learn probabilistic distributions for their parameters, offer a sound theoretical framework for estimating uncertainty. However, traditional hardware implementations of BNNs are expensive in terms of computational and memory resources, as they (i) are realized with inefficient von Neumann architectures, (ii) use a significantly large number of random number generators (RNGs) to implement the distributions of BNNs, and (iii) have a substantially greater number of parameters than conventional NNs. Computing-in-memory (CiM) architectures with emerging resistive non-volatile memories (NVMs) are promising candidates for accelerating classical NNs. In particular, spintronic technology, which is distinguished by its low latency and high endurance, aligns very well with these requirements. In the specific context of Bayesian neural networks (BNNs), spintronics technologies are very valuable, thanks to their inherent potential to act as stochastic or as deterministic devices. Consequently, BNNs mapped on spintronic-based CiM architectures could be a highly efficient implementation strategy. However, the direct implementation on CiM hardware of the learned probabilistic distributions of BNN may not be feasible and can incur high overhead. In this work, we propose a new Bayesian neural network topology, named SpinBayes , that is able to perform efficient sampling during the Bayesian inference process. Moreover, a Bayesian approximation method, called in-memory approximation , is proposed that approximates the original probabilistic distributions of BNN with a distribution that can be efficiently mapped to spintronic-based CiM architectures. Compared to state-of-the-art methods, the memory overhead is reduced by 8× and the energy consumption by 80×. Our method has been evaluated on several classification and semantic segmentation tasks and can detect up to 100% of various types of out-of-distribution data, highlighting the robustness of our approach, without any performance sacrifice.

Stochastic computing (SC) is an appealing approach to overcome the well-known limitations of traditional computing methods due to its smaller resource requirements and superior ability to handle noise. Ultimate CMOS-based stochastic circuits require considerable additional overheads and power consumption to generate and control the probabilistic bitstream. In this paper, we propose an innovative stochastic circuit that relies on superparamagnetic Tunnel Junctions, enabling concurrent sensing of the device as well as the tuning of the generated stochastic bitstreams. The proposed circuit is power efficient and shows robustness against process variations. The results demonstrate an improvement in the energy efficiency of up to x2 when compared to the related works.

Convolutional Neural Network (CNN) is one of the most important Deep Neural Networks (DNN) classes that helps solving many tasks related to image recognition and computer vision. Their classical implementations by using conventional CMOS technologies and digital design techniques are still considered very energy-consuming. Floating point CNN relies primarily on MAC (Multiply and ACcumulate) operation. Recently, cost-effective Bite-wise CNN based on XNOR and bit-counting operations have been considered as a possible hardware implementation candidate. However, the Von-Neumann bottleneck due to intensive data fetching between memory and the computing core limits their scalability on hardware. XNOR-BITCOUNT operations can be easily implemented by using In Memory Computing (IMC) paradigms executed on a memristive crossbar array. Among emerging memristive devices, the Spin-Orbit Torque Magnetic Random Access Memory (SOT-MRAM) offers the possibility to have a higher ON resistance that allows reducing the reading current, since all the crossbar array is read in parallel. This could contribute to a further reduction of energy consumption, paving the way for much bigger crossbar designs. This study presents a crossbar architecture based on SOT-MRAM with very low energy consumption; we study the impact of process variability on the synaptic weights and perform Monte-Carlo simulations of the overall crossbar array to evaluate the error rate. Simulation results show that this implementation has lower energy consumption with respect to other memristive solutions with 65.89 fJ per read operation. The design is also quite robust to process variations, with very low reading inaccuracies up to 10 %.

Several recent studies have proposed the utilization of emerging technology devices, such as ReRAM, spintronic, and phase change memory in hardware-implemented neural network designs. However, the current poor maturity of the manufacturing process of memristive devices limits the implementation of synapses to low precision weights and to smaller size crossbars, which could be an issue for complex, higher dimensions machine vector learning tasks (e.g., object recognition, classifications, etc). Face to these challenges, efficient hardware implementations use binarization for weights and activation functions in the attempt to reach better energy efficiency, reduce the utilization of memory and the execution time. Moreover, to compensate the immaturity of the emerging devices technology and achieve better convergence, accuracy, and speed for learning and inference process, the neural network has to be designed either with an increased degree of redundancy, or with error correction capabilities. To avoid the inherent hardware cost of the redundancy and counteract the aforementioned issues, we propose an approach combining the concept of Ensemble Neural Networks paradigm with analog in-memory hardware implementation with spin-orbit torque (SOT) spintronic devices. These devices are among the most power-efficient emerging technologies. The architectural performances, power, and accuracy are verified on several datasets, showing that these combined approaches allow not only a very good resilience to high bit error rates but also a great reduction in execution time and number of memory accesses with a further reduction of $\times 100$ for the energy consumption thanks to the SOT spintronic-based device.

In the age of automation, machine learning systems for real-time critical decisions in various domains such as autonomous driving are at an all-time high. Predictive uncertainty allows a machine learning system to make more insightful decisions by avoiding blind predictions. Algorithmically, Bayesian neural networks (BayNNs) based on dropout are principled methods for estimating predictive uncertainty in a machine learning application. However, the computational cost and power consumption make the use of BayNNs on embedded hardware unattractive. Hardware accelerators with emerging non-volatile resistive memories (NVMs) such as Magnetic Tunnel Junction (MTJ) in conjunction with quantized models are an interesting option for efficient implementations of such a system. Binary BayNNs are a desirable alternative that can provide predictive uncertainty efficiently by combining the benefits of quantization and hardware acceleration. In this paper, propose for the first time the binary bayesian neural network (BayBNN) using dropout-based approximation, and we leverage the inherent randomness of spin-tronic devices for in-memory Bayesian inference. Our proposed method can detect up-to 100% of the out-of-distribution data, improve inference accuracy by 15% for corrupted data, and ~ 2% for in-distribution data.