Minimum 18 nm pitch fully subtractive self-aligned Ru Topvia interconnects with embedded airgap have been demonstrated. It has been confirmed that Ru Topvia interconnects with Topvia trimming process can improve dielectric breakdown voltage between vias and adjacent lines, which is essential for future CMOS technologies. Moreover, in comparison to conventional damascene Cu interconnects with low-k, Ru top via interconnects with airgap provided a clear advantage, exhibiting 23% lower capacitance. Furthermore, excellent TDDB performance on subtractive Ru interconnects with 9 nm-space airgap has been obtained and superior EM performance of Ru Topvia interconnects has been achieved.

Fully subtractive TopVia Ru interconnects with embedded airgap have been demonstrated through spacer assisted litho-etch litho-etch (SALELE) patterning, which utilizes a novel spacer pull process to enable a wider design space than alternative spacer-is-metal (SADP-SIM) patterning approaches. Utilizing this approach, we have demonstrated good pattern fidelity and electrical yield for structures with minimum pitch at 18nm. Furthermore, we propose a novel “TopVia” structure, where the metallization for the via is performed together with the metallization for the line below, combined with an integrated airgap. The TopVia integration scheme enables a barrier-less/liner-less via structure leading to maximum conductor volume, with greatly reduced liner thickness at the via contact. Simulation results support significant reductions in both via resistance and capacitance can be achieved by replacing conventional Cu interconnects with Ru TopVia interconnects with airgaps. We believe the combination of a SALELE with spacer pull process and top-via with embedded airgap integration is one of the most promising integration schemes to enable a Ru conductor in future technology nodes.

Vertical-transport FET (VTFET) is a strong candidate for future CMOS technology. The concept of VTFET has been demonstrated in our previous report, which enables to scale logic area beyond sub-45nm contacted gate pitch (CGP). This paper focuses on performance assessment of VTFET based on hardware (HW). 1. 2x effective capacitance $(\mathrm{C}_{\mathrm{e}\mathrm{f}\mathrm{f}})$ contrasting to technology target is demonstrated based on 40CGP VTFET ring oscillator. Two major bottlenecks are identified as DC performance $(\mathrm{I}_{\mathrm{e}\mathrm{f}\mathrm{f}}$ at target $\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$) detractor. 90% DC performance compared to the target has been demonstrated by resolving the bottlenecks.

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. A(VT) of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

We discuss the effects of interface layers between high-k gate insulators and the Ge substrate on the electrical characteristics of Ge MOS devices. Our work has focused on both germanium oxynitride (GeOxNy) and tantalum oxynitride (TaOxNy) interface layers. We find that ultrathin interface layers of TaOxNy, a high permittivity diffusion barrier, produce greatly improved charge trapping characteristics and promising capacitance scaling for high-k/Ge gate stacks. Effects of interface layers on interface state density and the frequency dispersion of the capacitance-voltage (CV) behavior under inversion are also described.

We demonstrate that negative bias temperature instability (NBTI) of high-k (HfO2/SiO2) gate stacks are significantly improved by incorporating fluorine and engineering its concentration profile. We find that F piles up at HfO2/SiO 2 interface and diffuses into the underlying SiO2/Si interface. The HfO2/SiO2 stack with F shows significantly less CV hysteresis, positive charge trapping and interface states generation compared to control samples without F under the same negative bias condition. F is believed to form stronger Hf-F and Si-F bonds compared to Hf-H and Si-H bonds which improve the reliability of HfO2/SiO2

In this letter, we demonstrate that formation of a Zr-silicate interfacial layer between ZrO2 and Si substrate can be controlled by the solid state reaction between Zr and an underlying SiO2/Si substrate through in situ vacuum anneals and subsequent UV oxidation. By investigating the chemical shifts of Si2p, Zr3d, and O1s features using x-ray photoelectron spectroscopy, the formation of a Zr-silicide phase after in situ vacuum anneals of the Zr/chemical SiO2/Si gate stack at 200 °C was confirmed. The Zr-silicide was oxidized to form a Zr-silicate phase in the subsequent UV-ozone oxidation treatment. According to spectroscopic analyses, Zr-silicate bonding occurred in the interfacial layer for the in situ vacuum annealed samples. Vacuum annealed samples containing the silicate interface layer exhibited excellent dielectric characteristics, such as negligible capacitance–voltage hysteresis (∼10mV), lower fixed charge density, and reduced equivalent oxide thickness compared to unannealed samples.

We report the chemical bonding structure and valence band alignment at the HfO2∕Ge(001) interface by systematically probing various core level spectra as well as valence band spectra using soft x rays at the Stanford Synchrotron Radiation Laboratory. We investigated the chemical bonding changes as a function of depth through the dielectric stack by taking a series of synchrotron photoemission spectra as we etched through the HfO2 film using a dilute hydrogen fluoride solution. We found that a very nonstoichiometric GeOx layer exists at the HfO2∕Ge interface. The valence band spectra near the Fermi level in each different film structure were carefully analyzed, and as a result, the valence band offset between Ge and GeOx was determined to be ΔEv (Ge–GeOx)=2.2±0.15eV, and that between Ge and HfO2, ΔEv (Ge–HfO2)=2.7±0.15eV.

We have synthesized new crosslinkable functional polyesters derived from fumaryl chloride (FC) and Disperse Red 19 (DR-19). Preliminary experimental data demonstrated this is a convenient and inexpensive method for potential device fabrication. The optimum processing condition for a photocrosslinking nonlinear optical polymeric system was established.

We report on experimental studies of the interfaces formed between high-k metal oxide dielectrics and silicon and germanium (100) substrates. In one case, an oxygen-gettering Ti overlayer was used to decompose the SiO2 interface layer (IL) initially present between HfO2 films and Si, thus reducing the gate stack equivalent oxide thickness (EOT) after high-k deposition. The mechanism of SiO2 decomposition is described and electrical results obtained from MOSCAP structures are reported. In a second set of experiments, ZrO2/Ge and HfO2/Ge interfaces were systematically probed by photoelectron spectroscopy and transmission electron microscopy (TEM). Although it was possible to obtain chemically-abrupt interfaces by direct deposition of high-k metal oxide films onto Ge, capacitance-voltage (CV) measurements indicated significant charge trapping and high interface state density for stacks with no interface layer. We found that thermal nitridation to create a GeOxNy IL prior to high-k deposition significantly improved the capacitor electrical characteristics. Finally, spectroscopic determination of the band offsets between HfO2 and GeOx IL and a Ge substrate is reported.