We present the first Embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node. A novel integration supports the highest eMRAM density (0.0273 um2 cell size), optimal magnetic tunnel junction (MTJ) placement between M1-M2 for performance and density, and the lowest-cost integration scheme, with only 3 added mask levels (2 critical + 1 non-critical) and a single added electrode module. An advanced 400°C-compatible MTJ stack is read and written by innovative reference-cell sensing circuitry. We demonstrate digital functionality and write performance down to 4 ns, with companion parametric analysis for magnetoresistance, switching voltage, retention, and endurance cycling. Finally, we checked the 14 nm eMRAM hardware BEOL EM and TDDB at the critical levels, verifying good reliability after the embedding process.

Mechanically robust low k C-rich SiCN and pSiCN dielectrics with excellent built-in Cu oxidation and diffusion barrier have been developed and evaluated as potential alternative low k Interlevel dielectrics for Cu interconnects. The novel low k dense C-Rich SiCN (k=3.3) and lightly porous C-Rich SiCN (k=2.8) films have high modulus (E~> 15-30 GPa) and significantly lower Plasma Induced Damage (PID) as compared to typical pSiCOH (k~2.4-2.7) dielectrics. The excellent Cu diffusion barrier properties of these SiCN dielectrics enable the use of thinner metallic Cu barriers that resulting in larger Cu line’s volume, reduced resistance and overall improved RC in sub-50 nm pitch interconnects without TDDB and EM reliability penalty.

We investigate the performance and reliability characteristics of Cu interconnects with Ta-based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the impacts of reducing the Co thickness from 30 angstrom down to 10 angstrom. We demonstrate that while reducing Co liner thickness significantly reduces RC delay, there is a significant reduction in electromigration reliability below a thickness of 20 angstrom if used in conjunction with a PVD (physical vapor deposition) TaN barrier. However, if the PVD treatment is followed by deposition of a thin ALD (atomic layer deposition) TaN, the Co layer thickness can be scaled down to 10 angstrom without any penalty in either electromigration or time dependent dielectric breakdown (TDDB.) The combined PVD/ALD process with 10 angstrom Co enables a 14% reduction in RC delay relative to our control split.

Electromigration (EM) and TDDB reliability of Cu interconnects with a barrier/wetting layer as thin as 2 nm employing a PVD-reflowed through-Co self-forming barrier (tCoSFB) is demonstrated to meet the required specifications for 7 nm BEOL. The resulting Cu EM lifetime is 2000X longer than Cu interconnects with a standard scaled barrier/wetting layer. This tCoSFB Cu EM and TDDB reliability performance were equivalent to pure Co metal interconnects, but with a 50% lower line resistance even down to 30 nm pitch dimensions. However, the annealing process for PVD-reflow Cu seed that enhances EM reliability caused Cu agglomeration at dual damascene line-end vias, leading to poor via-chain yield. Resolving this geometry-sensitive via-fill problem was identified as key to extending Cu manufacturability to 7 nm and beyond. We propose, and show preliminary data, for Cu/tCoSFB metallization with CVD Co via pre-fill as potential solution.

Low resistance Cu interconnects with CVD Ru liner have been demonstrated for 7 nm node. Ru liner thickness reduction has been achieved by replacing PVD TaN with a bilayer PVD Ta and ALD TaN stack, while maintaining adequate Cu fill performance. The newly proposed barrier stack (PVD Ta/ALD TaN) with thin Ru liner studied in this paper also enabled a significant Ru CMP performance improvement by mitigating two major Ru CMP issues: Cu recess of narrow lines, and trench height variability between dense and isolated patterns. Furthermore, this novel barrier stack with Ru liner could attain void-free Cu fill even for beyond 7 nm node dimension. Thus, the PVD Ta/ALD TaN/CVD Ru liner is a promising candidate as the liner for Cu interconnects of 7 nm node and beyond.

For better gap fill in beyond 56nm pitch Cu interconnect structures, Ru liner is one of the most promising solutions with better coverage and wettability. In this paper several new challenges in Ru CMP specific to <= 48nm pitch structures (also called 10nm technology) are presented. New CMP solutions were developed by optimizing the slurry, consumables, and process sequence to address the observed challenges such as Ru bending and Cu recess. The optimized solutions to address these challenges were further tested on integrated wafers and improvements in resistance and yield were demonstrated through electrical tests. (C) The Author(s) 2018. Published by ECS.

SADP/SAQP are important patterning techniques for all the FEOL/BEOL line levels at 7 nm technology node and beyond. Therefore, an accurate CD and profile control of mandrel patterning is the key of a successful SADP/SAQP integration and an incorrect mandrel CD or profile could cause a huge loss due to wafer scrap. In this paper, a novel methodology utilizing multiple etch steps is presented to remove the incorrect patterning stack and to refresh the SADP patterning from the beginning. As a result, the misprocessed wafer could continue the process without loss. Two approaches were discussed in this paper. The results were showing that using dry etch to clear the mandrel stack instead of wet etch then took out the hard-masks and stopping on the IMD is the best way for removing the incorrect patterning stack. This methodology has been tested for up to three passes of refresh to verify the repeatability of both physical and electric data. In addition, a 34 passes prolonged test on the same wafer was conducted over a year showing successful refreshes with consistent physical CD.

Several major electron scattering mechanisms in tungsten (W) are evaluated using a combination of first-principles density functional theory, a Non-Equilibrium Green's Function formalism, and thin film Kelvin 4-point sheet resistance measurements. The impact of grain boundary scattering is found to be roughly an order of magnitude larger than the impact of defect scattering. Ab initio simulations predict average grain boundary reflection coefficients for a number of twin grain boundaries to lie in the range r = 0.47 to r = 0.62, while experimental data can be fit to the empirical Mayadas-Schatzkes model with a comparable but slightly larger value of r = 0.69. The experimental and simulation data for grain boundary resistivity as a function of grain size show excellent agreement. These results provide crucial insights for understanding the impact of scaling of W-based contacts between active devices and back-end-of-line interconnects in next-generation semiconductor technology.

We present a combined theoretical and experimental study on the electron transport characteristics across several representative interface structures found in back-end-of-line interconnect stacks for advanced semiconductor manufacturing: Cu/Ta(N)/Co/Cu and Cu/Ta(N)/Ru/Cu. In particular, we evaluate the impact of replacing a thin TaN barrier with Ta while considering both Co and Ru as wetting layers. Both theory and experiment indicate a pronounced reduction in vertical resistance when replacing TaN with Ta, regardless of whether a Co or Ru wetting layer is used. This indicates that a significant portion of the total vertical resistance is determined by electron scattering at the Cu/Ta(N) interface. The electronic structure of these nano-sized interconnects is analyzed in terms of the atom-resolved projected density of states and k-resolved transmission spectra at the Fermi level. This work further develops a fundamental understanding of electron transport and material characteristics in nano-sized interconnects.

The impacts of ruthenium and cobalt liners on copper resistivity have been investigated at beyond 7nm dimensions. Liner metal conduction was carefully evaluated in a Cu resistivity derivation using the temperature coefficient of resistivity (TCR) approach. Cu resistivity with Ru liner is higher than with a Co liner by 10-15%, which is verified by RC plot. The resistivity difference is attributed to interface scattering and possibly grain boundary scattering. Interface ab initio calculations show 3-7% increase of Cu resistivity from Co liner to Ru liner.

As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating voltage is now limited by Vx to Mx spacing. This spacing has historically been a challenge since the introduction of self-aligned vias due to the loss of CD and chamfer control in the non-self-aligned direction. As pitch continued to shrink from self-aligned via introduction around the 22 nm node, the fraction of via CD control and edge placement compared to the dielectric spacing between interconnects has continued to grow. Alone this trend could be combated by increasing the dielectric spacing, however, the exponential increase in Cu resistivity (under scaling) has forced BEOL technologies into strong line/space asymmetry to keep line resistance under control. At pitches below 32 nm these factors reach a tipping point, either design to exponentially increasing line resistance or lower the technology Vmax. Both approaches cause performance degradation to achieve pitch scaling

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Co/Cu composite interconnect systems were studied. Since wide Cu lines require a diffusion barrier which is simultaneously applied also to fine Co lines to reduce Co volume fraction, through-Cobalt Self-Formed-Barrier (tCoSFB) was employed to thin down TaN barrier to <1 nm which works as an adhesion layer for Co lines. Line R of fine Co lines was reduced by 30% successfully. The Co/tCoSFB-Cu composite interconnect system is promising to achieve low line R for both fine and wide lines simultaneously in 7nm BEOL and beyond.

Cobalt and copper interconnects with identical barrier and CMP processes were formed on ultra-low k (ULK) dielectric films at the 7nm node. Divot-free Co and Cu interconnects are demonstrated using the same CMP process. Co-filled dual damascene interconnects show high line yields with similar via resistance values compared to Cu. Co line resistance measures three times higher resistance than Cu. The resistivity of Co and Cu lines is calculated by measuring line resistance and cross-sectional area by transmission electron microscopy (TEM). Measured via resistance of the dual damascene Co-filled via is only 10% higher than the Cu-filled via control. Thus by scaling or even eliminating traditional Cu barriers in the via, Co can be a valid Cu replacement candidate for via fill.

Microstructure variation with post-patterning dielectric aspect ratio (AR) and post-plating annealing temperature has been investigated in Cu narrow wires. As compared to the conventional annealing at 100 °C for a feature AR of 2.6, both elevated temperature anneals and reduced AR structures modulated Cu microstructure, which then resulted in a reduced rate of electrical resistivity increase with area scaling and an increased electromigration resistance in the Cu narrow wires.

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

Line resistance reduction in interconnects was achieved through Cu microstructure modulation. The modulation was performed via both raising annealing temperature and reducing the post-patterning dielectric aspect ratio and resulted in a bamboo-like Cu microstructure. Compared with the conventional polycrystalline, the modulated Cu microstructure also presents a lower resistivity increase rate with area scaling. A TaN stress control layer deposited on over-plated Cu surface was demonstrated to be critical for maintaining the Cu interconnect integrity after the high-temperature anneal.

Adhesion tests, parametric measurements, and reliability evaluations of an in-situ pre-liner dielectric nitridation process prior to pure Ta liner deposition were carried out, to evaluate the feasibility of reducing via resistance in BEOL Cu/low-k interconnects. Replacing TaN/Ta with Ta in the conventional liner stack reduces Cu via resistance, while the nitridation treatment maintains Cu interconnect integrity and reliability.