FeRAM is a promising candidate for next generation embedded DRAM and has attracted significant attention with the advancements in hafnia-based ferroelectric research. In this work, we will review record specifications achieved for implementing FeRAM as an embedded memory such as 2 nanoseconds switching speed, >10 12 read/write endurance cycles, low operation voltage, long retention, and operation under worst case anti-ferroelectric (AFE) capacitors process variations at elevated temperature of 85°C. Array-level circuit simulation based on the advanced technology node also indicates that FeRAM can be used as a high-density embedded memory. Finally, functional 3D stacked AFE capacitors with matched performance to conventional trench AFE capacitors are demonstrated for the first time paving the path toward ultrahigh density embedded FeRAM.

An overview of three-dimensional integrated circuits (3D ICs) is presented in this paper. The key potential applications of 3D ICs that have the most impact in terms of performance, power and area are highlighted, followed by a brief overview of the different technology approaches to implement 3D ICs. Further, the key challenges to 3D integration are discussed here.

3-D integration using through-silicon vias (TSVs) can decrease interconnect length and improve chip performance. In this paper, electrical links consisting of TSVs and horizontal wires are designed, fabricated, and measured to analyze TSV capacitance and link delay. Compact models for the capacitance of a TSV surrounded by variable number of ground TSVs are developed and compared with measurements. The impact of TSV placement and scaling on link performance is further analyzed. The results demonstrate that placing TSVs closer to their drivers can effectively improve the performance of 3-D integrated circuit (3-D IC) links. Moreover, link delay is significantly improved by scaling TSV geometry to the point that 3-D IC links become on-chip wire limited.

Frequency and time domain models are developed for backplane (BP), printed circuit board (PCB), and silicon interposer (SI) links using six-port transfer matrices (ABCD matrices) for bumps, vias and connectors, and coupled multiconductor transmission lines for traces. The six-port transfer matrix approach enables easy computation of the transfer function, as well as near-end and far-end crosstalk. The intersymbol interference is accounted for by computing the pulse response for the worst case bit pattern. Furthermore, the models developed here are used to optimize the data-rate and trace width for each of the links, so that the aggregate bandwidth obtained per joule of energy supplied to the link is maximized. The modeling and optimization approach developed here serves as a good platform to compare the air-gap interconnects against BP, PCB, and SI interconnects on lossy dielectrics. It is shown that air-gap interconnects can provide an aggregate bandwidth improvement of 3x-4x for BP links at a comparable energy per bit, and a 5x-9x improvement in aggregate bandwidth of PCB links at the expense of 20% higher energy per bit. For SI links, airgap interconnects are shown to provide a 2x-3x improvement in aggregate bandwidth and a 1x-1.5x improvement in energy per bit.

Stochastic wiring distribution models are used to predict the improvement in energy obtained by replacing a few or all copper metal levels with graphene nanoribbons (GNRs) in a low-power digital circuit. The models developed here also estimate the degradation in the performance by replacing a few or all copper metal levels with GNRs. Replacing a few local copper interconnect levels with GNRs is expected to reduce the energy consumed by local interconnects, without severely degrading the performance of longer global interconnects. The hybrid GNR+copper interconnect is shown to perform worse compared to the all GNR interconnect, if the length of the GNR segment is greater than a critical value. For a logic circuit with 30k gates, it is shown that the hybrid interconnect offers a 30 to 40% decrease in energy and a 4× decrease in maximum frequency, whereas the all GNR interconnect offers a 50 to 60% decrease in energy and a 7× decrease in maximum frequency. Further, the impact of edge doping on the resistance per unit length of graphene is analyzed.

This paper presents the major limitations to the interconnect technology scaling at future technology generations and demonstrates both evolutionary and radical potential solutions to the BEOL scaling problem. To address the local interconnect challenges, a novel hybrid Al-Cu interconnect technology is introduced. Performances of carbon-based interconnects are evaluated as a more radical solution. The impact of interconnects and the optimal interconnect options are investigated for emerging next generation devices. Interconnects for new state variables, namely spintronic interconnects, are studied and their potential performances in an all-spin logic system are evaluated.

In this paper, emerging low-power interconnect options for CMOS and beyond CMOS technologies are reviewed. First, electrical interconnects based on carbon nanotubes and graphene nanoribbons are discussed. It is found that carbon-based electrical interconnects can potentially outperform their conventional Cu counterpart at technology nodes close to or below 10 nm. Next, since using electron spin as a novel state variable has attracted major attention, interconnect options for beyond-COMS spintronic devices will be discussed. We start with metallic interconnects based on the non-local spin-valve and spin-torque-driven switching, and the impact of size effects and dimensional scaling on their potential performance is studied. It is found that the spin signal in the non-local structure decays significantly because of a large degradation in the spin relaxation length as the interconnect width decreases. Next, a spintronic interconnect in the form of a conventional spin-valve configuration is introduced to increase the energy efficiency by eliminating the loss of spins in the non-local structure. Both metallic and semiconducting channels are studied, and the results show that the metallic interconnect is more energy-efficient than the semiconducting one when the interconnect is short (a few hundreds of nanometers) due to a high conductive current path. However, a semiconducting channel is appropriate for an intermediate or long (several microns) interconnect due to a longer spin relaxation time and the possibility of using an electric field to enhance the spin relaxation length. Furthermore, it is shown that for spin interconnects, downscaling the size of the ferromagnets can largely reduce the delay, energy, and energy-delay product at the cost of a shorter retention time.

In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical-horizontal transitions. The motivation is to create an air-gap technology that offers the lowest possible effective k-value and near zero loss tangent minimizing the dielectric loss. The design and modeling of air-gap interconnection is presented. The fabrication challenges in air-clad interconnect lines are discussed. A monolithic inverted air-gap horizontal transmission line structure is proposed as a means for further decreasing the dielectric loss. Extension of air-clad TSV technology for optical transmission is briefly discussed.

Interconnects are considered as one of the grandest challenges that gigascale and terascale integrations face because of the delay they add to critical paths, the power they dissipate, the noise and jitter they induce on one another, and their vulnerability to electromigration. Recent studies on novel computational state variables such as electron spin have demonstrated that interconnects will continue to be an ever-growing challenge, even for post-complementary metal-oxide-semiconductor (CMOS) switches. The novel 2-D carbon-based material graphene has demonstrated remarkable electrical properties that make it a viable candidate to implement interconnects in both electrical and spintronic domains. In this paper, physical models of the electron transport parameters such as electron mean free path (MFP), diffusion coefficient, mobility, and resistance per unit length are presented for both bulk (2-D) and narrow (1-D) graphene nanoribbons (GNRs) as a function of the interconnect dimensions, edge roughness, and Fermi-energy shift. The potential of multilayer GNR (ML-GNR) as electrical interconnects is explored by taking into account the finite interlayer resistivity between the multiple layers within the ML-GNR stack. The spin-relaxation length in graphene is obtained using some theoretical estimates on the spin-orbit coupling (SOC) introduced due to ripples in graphene. It is found that, in pure graphene, the spin-relaxation length could be longer than 10 μm; however, the presence of adatoms limits the spin-relaxation length in graphene to only 1-2 μm at room temperature. The models developed in this paper are used to benchmark graphene interconnects against their conventional copper/low- κ interconnects in both electrical and spintronic domains. The results offer important insights about the advantages and limitations of graphene interconnects and provide guidelines for technology development for this emerging interconnect technology.

A review of the analytical models for signal transport in multi-layer graphene nanoribbon (GNR) interconnects, current distribution between GNR layers, and a comparison of GNR interconnects against copper is presented here. The multiconductor transmission line (MTL) models and the simplified equivalent distributed RC models presented here consider the realistic effect of having contacts that couple only to the top layer. The MTL models are used to show the distribution of current among different layers along the interconnect length. For digital circuits and interconnect dimensions of interest, it is shown that the equivalent RC models have an error of less than 15% in estimating the interconnect delay. However, for RF circuits where the accurate frequency response is important, it is shown that MTL models are essential. The optimal number of GNR layers to minimize the delay and energy-delay-product (EDP) are derived using the distributed RC models for futuristic technology nodes. Using the predictions made by the International Technology Roadmap for Semiconductors (ITRS), it is shown that for short interconnects, multi-layer GNR with smooth edges can outperform copper.

This paper quantifies the challenges, limits, and opportunities of interconnects for evolutionary and revolutionary semiconductor technologies of the future. Various exploratory devices and the delays associated with their transport mechanisms are quantified. Graphene is selected as the interconnect material of choice because of its excellent transport properties over the conventional Cu/low-K: interconnects currently serving as the communication medium in integrated circuits. Compact models that describe the transport properties in graphene (electron mean free path, mobility, spin relaxation) are presented. These compact models are used to (i) evaluate the performance and energy-per-bit of graphene interconnects in electrical and spintronic domains and (ii) compare these metrics against those of conventional electrical interconnects at the end of silicon roadmap technology node (minimum feature size of 7.5 nm).

This paper presents the first optimization methodology for silicon interposer interconnect technology. The dimensions of these fine-pitch interconnects are roughly a few microns, because of which they can neither be treated as on-chip RC interconnects, nor as conventional off-chip interconnects. 3D extraction tools can provide an accurate estimate of the circuit parameters, but they prove to be very slow and tedious for design space exploration and optimization. Thus, the novel analytical models developed here for the frequency dependent resistance of fine-pitch interconnects are essential to efficiently optimize these interconnects. The error in the model is shown to be less than 15% for interconnect dimensions and frequency range of interest. The analytical models developed are then used to optimize the data-rate and cross-sectional dimensions to maximize the bandwidth-density and minimize the energy-per-bit, simultaneously.

In this paper we present a compact model for analysis of 3D chip-to-chip interconnect pathways consisting of planar transmission lines, vias, package and pin discontinuities. The model accurately captures signal losses for a wide frequency spectrum with very small error when compared with HSPICE circuit simulations. The interconnect pathway is optimized for maximum bandwidth density and minimum energy-per-bit highlighting the performance improvement obtained using low-k, air-clad planar interconnects over conventional substrate materials.

With continued shrinking of device dimensions on chip, major advancements in intra chip interconnect technology are required to minimize delay, energy dissipation and cross-talk. In this paper, two alternative on-chip interconnect technology options are studied, namely the plasmonic and optical interconnects. It is shown that plasmonic interconnects can be 3 orders of magnitude faster than minimum sized CMOS interconnects at the 2016 technology node. However, their propagation length is limited to few microns and hence they can be used only as short local interconnects. Energy per bit of plasmonic interconnects is shot-noise limited and it increases exponentially with interconnect length. Cross-over length beyond which plasmonic interconnects become less energy efficient compared to CMOS interconnects is calculated. It is found to be 10 μm for Ag cylindrical plasmonic waveguides of 100-nm diameter embedded in SiO2 dielectric at free-space wavelength of 1μm. Although plasmonic interconnects show potential as future local interconnects, plasmonic switches are needed for their implementation at the GSI(GigaScale Integration) level. Without plasmonic switches the energy and circuit overhead associated with signal conversion will be prohibitive. Optical interconnects, on the other hand, are limited to be used only at the global level due to the fundamental limitations on their size. Although the native interconnect delay of optical interconnects is quite less, their bandwidth density is limited due to the fundamental limitations on the minimum pitch. Wavelength division multiplexing is identified as one of the solutions towards increasing the bandwidth density of optical interconnects. Critical length beyond which optical interconnects offer higher bandwidth compared to copper interconnects is identified to be equal to the chip edge in absence of WDM. In presence of 4 channel WDM, the critical length improves to 0.4cm. Critical length assessment based on energy comparison with CMOS interconnect is evaluated to be 0.15cm.

In this paper, physical models are derived for the effective resistance of multilayer graphene nanoribbon (m-GNR) interconnects. The impact of finite resistive coupling between the layers for top contacted m-GNR interconnects is considered. It is found that the addition of more parallel layers does not necessarily translate into a decrease in the overall resistance of m-GNR interconnects. Rather, the improvement in the effective resistance saturates with an increase in the number of layers. The optimal number of layers to minimize the delay and the energy-delay product of m-GNR interconnects is also evaluated. It is found that the optimal number of layers is a function of the interconnect length, interlayer resistance, and the kind of contact that is used. It is demonstrated that, for short interconnect lengths, m-GNR interconnects with smooth edges perform better compared to copper wires.