In this study, flow boiling of refrigerant R245fa is investigated in a microgap of height 200 mu m populated with a staggered pin fin array of diameter 150 mu m and spacing 200 mu m. For heat fluxes up to 498 W/cm(2), mass flux values up to 7896 kg/m(2) s, and inlet temperatures of 13 degrees C and 18 degrees C, average two-phase heat transfer coefficient up to 60 kW/m(2) K are measured. High speed flow visualizations at frame rate of 2229 fps elucidate the flow boiling patterns inside the microgaps, including bubbly and foggy that are generated in the pin finned area. Surface temperatures are measured for heat fluxes up to 498 W/cm(2) which enable determination of heat transfer characteristics. (C) 2018 Elsevier Ltd. All rights reserved.

A high-density and a highly scalable heterogeneous multi-die integration technology is presented in this paper. Central to this approach is a dense and face-to-face integration of heterogeneous ICs enabled by fine-pitch and multi-height compressible microinterconnects (CMIs) and stitch chips, which serve as the interface through which communication between active ICs occurs. Two separate testbeds are fabricated in order to characterize the proposed integration technology: the first testbed demonstrates the concatenated assembly of chips using the stitch chips with fine-pitch CMIs (in-line pitch of 20 mu m), while the second testbed demonstrates the fabrication of multi-height CMIs (75-, 55-, and 30-mu m tall CMIs) on the same die. Electrical characterization, including resistance and S-parameters, and mechanical characterization of interconnects are reported as well as the assembly of the testbeds.

In this paper, a Heterogeneous Interconnect Stitching Technology (HIST) is reported. In the proposed approach, stitch-chips, which may be active or passive chips, are placed between the package substrate and concatenated 'anchor chips'. Fine-pitch Compressible MicroInterconnects (CMIs) are used to provide low-loss and robust interconnection between the anchor chips and the stitch-chips. The CMIs are also used to compensate for any package non-planarity and stitch-chip thickness variations, as one anchor chip may interface to multiple different stitch-chips at each of its edges. Electrical measurements of the assembled chips are reported and demonstrate robust interconnection. Integrated circuits in the HIST platform are thermally evaluated to investigate thermal challenges and opportunities for such multi-die packages. Impact of different parameters, including die-spacing, stitch-chip splitting, and die-thickness mismatch, for example, on the thermal profile are evaluated. Moreover, power delivery network analysis is performed for the HIST platform with focus primarily on the IR-drop as a function of the overlap area between the anchor dice and the stitch-chips.

A high-density and a highly scalable heterogeneous multi-die integration technology is presented in this paper. Central to this approach is the dense integration of heterogeneous ICs enabled by fine-pitch Compressible MicroInterconnects (CMIs) and stitch chips, which serve as the interface through which communication between active ICs occurs. A testbed is fabricated in order to characterize and demonstrate the proposed integration technology: concatenated assembly of chips using the stitch chips with fine-pitch CMIs (inline pitch of 20 μm). Electrical characterization, including resistance and S-parameters, of the interconnects are reported as well as the assembly of testbeds. The measured results show robust and low-loss interconnections across multi-chips.

In this paper, compact circuit models and HSPICE simulations are used to benchmark die-to-die communication channels in 2.5-D and 3-D heterogeneous integration platforms. The delay, energy-per-bit, and bandwidth-density of the considered integration platforms are simulated and benchmarked. Compared to other 2.5-D integrated systems with a 1-mm interconnect length, heterogeneous interconnect stitching technology (HIST)-based 2.5-D integration shows a maximum latency and energy reduction of 6.2% and 15.1%, respectively. 3-D ICs show further performance enhancement compared to 2.5-D integration; the link latency and energy are approximately 19.4% and 48.0% smaller than those of HIST (1-mm wire) for through-silicon via (TSV)-based 3-D integration (75-mu m TSV height). Next, the impacts of the physical I/O interconnect dimensions and device process technology scaling are evaluated and we observe that advanced process technologies must be integrated with smaller physical I/O dimensions and shorter wire lengths to attain full advantages of scaling. Finally, we consider the thermal impact of dense heterogeneous integration and investigate the thermal and electrical signaling tradeoffs in 2.5-D and 3-D integration.

As power demands for microelectronic devices continue to rise, new techniques for heat dissipation require innovative fabrication solutions such as on-chip cooling methods. The mechanical reliability of these high-powered, high-pressure systems is particularly sensitive to the interfacial strengths within the microelectronic architectures. In research at Georgia Tech, on-chip cooling methodologies involve cooling of devices with high-pressure coolant which is pumped through a microchannel. The microchannels are etched directly into a silicon wafer and then capped by a second wafer of pyrex glass. When fluid flows through the system, internal pressures can exceed 2000 kPa in certain locations of the microchannel. Overall system failure due to cracking of the brittle materials is of particular interest given the potential for catastrophic crack propagation. Using a combination of experiments and modeling, a methodology for predicting interfacial and cohesive strength of the silicon-glass bonded microchannel system has been developed. The objective of this work is to demonstrate the results of the experimental test technique and to extract appropriate silicon-glass interfacial test data in conjunction with numerical modeling of the fracture conditions.

Understanding two-phase convective heat transfer under extreme conditions of high heat and mass fluxes and confined geometry is of fundamental interest and practical significance. In particular, next generation electronics are becoming thermally limited in performance, as integration levels increase due to the emergence of 'hotspots' featuring up to ten-fold increase in local heat fluxes, resulting from non-uniform power distribution. An ultra-small clearance, 10 mu m microgap, was investigated to gain insight into physics of high mass flux refrigerant R134a flow boiling, and to assess its utility as a practical solution for hotspot thermal management. Two configurations - a bare microgap, and inline micro-pin fin populated microgap - were tested in terms of their ability to dissipate heat fluxes approaching 1.5 kW/cm(2). Extreme flow conditions were investigated, including mass fluxes up to 3000 kg/m(2) s at inlet pressures up to 1.5 MPa and exit vapor qualities approaching unity. Dominant flow regimes were identified and correlated to two phase heat transfer coefficients which were obtained using model based data reduction for both device configurations, The results obtained were compared to predictions using correlations from literature, with the maximum heat transfer coefficient reaching 1.5 MW/m(2) K in the vapor plume regime in the case of the finned microgap. (C ) 2016 Elsevier Ltd. All rights reserved.

In this paper, two integration technologies are discussed for heterogeneously integrated microsystems. First, this paper presents low-loss TSVs using an air-isolation technique for silicon interposers. The proposed air-isolated TSVs exhibit approximately 35% and 37% reduction in insertion loss and capacitance, respectively, at 20 GHz. Moreover, this paper presents a TSV-less integration technology using bridge chips and Compressible MicroInterconnects (CMIs). Compared to other packaging and assembly options, the investigated TSV-less approach provides monolithic-like electrical performance by significantly reducing chip-to-chip interconnect length and loss, increasing interconnect density, and providing the ability to seamlessly integrate chips of diverse functionalities.

In this letter, a heterogeneous interconnect stitching technology is proposed. Stitch chips with high-density fine pitch wires are placed between the substrate and the active chips. Fine-pitch microbumps are used to bond the chips and provide high density and low-energy signaling. Compressible microinterconnects (CMIs) are used to compensate for package non-planarity and enable chip-package interconnection. A testbed with two passive chips and one stitch chip was fabricated and assembled. The post-assembly electrical resistance values of the microbumps and CMIs, as well as the mechanical compliance of the CMIs, are measured. The resistance of the microbumps ranges from 77.8 to $188.3~\mu \Omega $ and the resistance of the CMIs ranges from 141.2 to 252.9 $\text{m}\Omega $ . The mechanical compliance of the CMI is approximately 13.7 mm/N with a vertical elastic deformation of up to $30~\mu \text{m}$ .

As the need for high performance and extreme power-dissipation microelectronic devices continues to rise, innovative thermal management solutions are being developed to efficiently remove the high heat fluxes dissipated in these applications. At heat flux rates surpassing the 1000 W/cm2 level in some localized hot spot cases, conductive spreading to an external heat sink is no longer a viable thermal management option. On-chip, enhanced microfluidic cooling with pin fins offers new opportunities to deliver coolant in close proximity to power dissipation zones and hot spots. In state-of-the-art designs a two-phase refrigerant is pumped through a microfluidic channel within an active device absorbing heat at high velocity. Hydrofoil-shaped, silicon micro-pin fins populate the flow space to increase surface area available for heat removal and for liquid films to coalesce. The proposed thermal-management system has been fabricated by etching the microchannel with hydrofoil pin fins into the backside of the silicon device and then bonding it to a capping layer. While the hydrofoil shape is designed to benefit thermal-fluid performance properties, reliability consideration must also be given to the geometry. Phase change of the liquid facilitates optimal heat removal rates but also requires high-pressure conditions for operation. At these high-pressure conditions, the pin fins will be subjected to stress due to fluid pressure. Because of the unique geometry of the hydrofoil pin fins, special consideration must be given to the interaction of stress concentrations due to fluidic pressure loading and the small radius of curvature of the hydrofoil tail. The objective of this paper is to examine the various sources of stress in this high-performance, micro-pin fin channel and explore the reliability of this hydrofoil pin fin design under high-pressure conditions.

We present an experimental study of two phase flow of refrigerant R245fa in a pin fin enhanced microgap for a range of heat fluxes between 151 W/cm 2 to 326 W/cm 2 . The gap has a base surface area of 1cm × 1cm and height of 200 μm. An array of hydrofoil shaped pin fins covers from bottom to top of the microgap. The pin fins have chord length, longitudinal pitch, and transversal pitch of 75μm, 450μm and 225μm, respectively. On the back side of the chip, four platinum heaters are fabricated and electrically powered in series to enable two phase flow in the microgap, which was part of a pumped flow loop. Heater and surface temperature data were obtained versus heat flux dissipated. Flow visualization was performed using a high speed camera in the heat flux range from 151 W/cm 2 to 326 W/cm 2 . The amount of heat loss across the test section is also provided.

In this paper, the impact of microfluidic cooling on the electrical characteristics of through-silicon vias (TSVs) is investigated for three-dimensional (3-D) integrated circuits (ICs). The design and fabrication of a testbed containing TSVs are presented for two types of heat sinks (micropin-fin and microchannel heat sinks) immersed in deionized (DI) water. The high-frequency characterization of TSVs in the DI water-filled testbed is performed and compared to conventional TSVs in silicon. TSVs in DI water demonstrate higher insertion loss, capacitance, and conductance than TSVs in silicon. In this paper, we also present coaxially shielded TSVs embedded in a pin-fin heat sink and demonstrate the electrical isolation of the signal TSV from the surrounding DI water.

3-D integration using through-silicon vias (TSVs) can decrease interconnect length and improve chip performance. In this paper, electrical links consisting of TSVs and horizontal wires are designed, fabricated, and measured to analyze TSV capacitance and link delay. Compact models for the capacitance of a TSV surrounded by variable number of ground TSVs are developed and compared with measurements. The impact of TSV placement and scaling on link performance is further analyzed. The results demonstrate that placing TSVs closer to their drivers can effectively improve the performance of 3-D integrated circuit (3-D IC) links. Moreover, link delay is significantly improved by scaling TSV geometry to the point that 3-D IC links become on-chip wire limited.

This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 μm and pin diameters of 90 μm and 30 μm. Single-phase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm2 to 470 W/cm2. The maximum heat transfer coefficient reached was 60 kW/m2 K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design.

In this paper, we explore the design considerations of two approaches to 2.5-D integration (silicon interposer and bridge-chip) from a thermal perspective and compare to 3-D ICs. Moreover, the impact of die thickness mismatch and die spacing are investigated in 2.5-D systems. We conclude that the die dissipating the largest power should be the thickest in a multi-die package. Larger lateral spacing between dice reduces the temperature at the unrealistic expense of communication power efficiency. Therefore, it is necessary to consider this tradeoff when selecting appropriate die spacing.

The presence of variable heat fluxes, such as localized hotspots in integrated circuit (IC) architectures poses a key challenge for thermal management of existing (2D) and emerging three-dimensionally (3D) stacked chips. The use of conventional microchannel or uniform pin fin arrays for microfluidic cooling do not provide adequate surface area for heat transfer in the vicinity of regions of concentrated high power (hotspots), and therefore significant temperature gradients might arise in such zones. In the present investigation, the concept of using a single microfluidic loop for the combined and efficient cooling of hotspot and moderate power (background) areas is proposed, experimentally demonstrated, and supported by a comprehensive numerical model. Two different thermal device vehicles (TDVs) are considered for a range of operating conditions, in which the surface area is locally increased by clustering a dense array of pin fins in the hotspot region for one configuration, while for the other the clustering is uniform in the spanwise direction. De-ionized (DI) water is used as the coolant through a silicon (Si) microgap with 200 tm spacing; the hotspot heat flux is varied from 250 to 750 W/cm(2), while the background heat flux is fixed at 250 W/cm2. Results indicate the capability of the proposed designs to keep the maximum temperature of the combined device below 65 degrees C for an inlet water temperature of 21.3 degrees C, with moderate temperature gradients and pressure drop. In addition, a robust computational fluid dynamics/heat transfer (CFD-HT) model capable of predicting spatially resolved temperature fields arising from heterogeneous heating is validated with relevant experimental data. Detailed benchmark simulations are provided, so they can be reproduced and used for reference in numerical studies with variable pin fin densities. The described methodology represents a cost-effective thermal modeling technique that may be applicable to virtually any type of heat flux distribution or power map, and IC architecture. (C) 2016 Elsevier Ltd. All rights reserved.

In this work, we designed, fabricated and characterized a novel hotspot testbed to dissipate ultra-high power density by two-phase convective boiling of refrigerant in a microgap with integrated micropin-fins and isolation air trenches around resistance heaters. The 300 µm long, 200 µm wide, and 10 µm tall microgap with 4 µm diameter micropin-fins was batch micro-fabricated in silicon. The 40 µm wide and 180 µm deep isolation air trenches around the heater and a SiO2 passivation layer were used to provide thermal isolation. The testbed dissipates a power density of up to 4.75 kW/cm2 using R134a refrigerant as the coolant. Thermal resistance and pumping power were compared between the micropin-fin device of interest and a reference ‘empty microgap’ device to assess tradeoffs in performance. Micropin-fins were found to slightly reduce thermal resistance at the cost of a large increase in pumping power. In addition to experimental work, thermomechanical simulations were implemented to analyze the reliability of the device for high pressure conditions.

Performance of the next generation microprocessors is rapidly reaching its limits due to inability to remove heat, especially at high power density from so-called local “hotspots”. Convective boiling heat transfer in microgap heat sinks has the potential to dissipate ultra-high heat fluxes. We report results of an experimental investigation of heat transfer performance of three dedicated microgap coolers for hotspot thermal management. In this study, a rectangular microgap, batch micromachined in silicon and instrumented with thin-film resistive thermometry, is employed to assess its capability of dissipating extreme heat fluxes of multiple kW/cm2 while keeping the wall temperature within the limits dictated by electronics reliability. Convective boiling in microgap with heights of 5 µm and 10 µm was tested with and without pin fins in the microgap. The test section was heated from the bottom using resistive heaters and capped with glass to enable visual observation of two-phase flow regimes. Microgap pressure drop and wall temperature measurements, mapped into flow regimes, were obtained with R134a as the coolant, for heat fluxes up to 5 kW/cm2, mass fluxes up to 7,000 kg/m2s, at maximum pressures up to 1.5 MPa and outlet vapor qualities approaching unity. These experimental parameters constitute extreme values in terms of microgap height (smallest reported to our knowledge), mass fluxes, and heat fluxes. New flow regimes, including vapor plumes, liquid slugs, and ultra-thin wavy liquid film, were observed as a function of increasing heat flux and microgap geometry. Dominant mechanism(s) of two-phase heat transfer responsible for each regime have been postulated based on flow visualization correlated with pressure drop and thermal resistance measurements.