A wideband subsampling track -and-hold amplifier has been designed for input frequencies Up to Ku-band and clock rates up to 2.5 GS/s. Circuits were fabricated in 1 mu m InP SHBT technology. Spur-free dynamic range measured with two-tone input frequencies of 12.6 and 12.602 GHz and a 2.5 GS/s clock rate ranges from 53-69 dB at an input level of-1 dBFS for each tone. Signal-to-noise ratio (SNR) test results show that the master/slave (M/S) track-and-hold design provides 59 dB of SNR in a 1 GHz bandwidth at input frequencies up to at least 2.6 GHz. A single track-and-hold dissipates 1.5 W while the M/S configuration dissipates 2.5 W.

A track-and-hold (T/H) circuit which was implemented with antimonide based compound semiconductor (ABCS) HBTs operated at 6 GS/s and consumed 478 mW. With a 600 MHz, 300 mV peak-to-peak input, the fundamental to 3(rd) harmonic ratio was measured to be 43 dB. It represents a power saving of at least a factor of 2 for the T/Hs of similar performance as compared with any other semiconductor technology.

A 10.24GSPS photonic sampled DeltaSigma modulator was implemented with HRL laboratories InP HBT process. The 12GHz analog input is sampled by a LiNbO3 optical modulator with a 10.24GHz ultra-low jitter mode-locked laser. The intensity-modulated differential laser pulses are converted into electronic charges by on-chip GaInAs photo diodes and directly integrated into the first stage integrator of a 4th-order continuous-time bandpass DeltaSigma modulator with a passband centered at 1.8GHz. The high notch frequencies of the DeltaSigma ADC are achieved by using a special type of integrator. This ADC achieves 59.9dB SNDR in 1MH bandwidth with 1263 InP HBT transistors

This paper summarizes our recent work on high-speed photonic analog-to-digital conversion (A/D) technologies, where picosecond pulses generated by a 10 GHz mode-locked laser source were used to accomplish low-jitter photonic sampling. In addition, we describe our progress in the generation of 40 GHz wavelength-coded pulses for time-interleaved A/D, and the demonstration of photonic bandpass (at 1.6 GHz) Δ-∑ quantizers clocked at 10 GHz.

A 5th-order continuous-time switched-current ΣΔ modulator was implemented in a 0.6µm CMOS process. A high sampling speed was achieved by using open-loop continuous-time integrators and differential current switches. The performance was optimized by using a 6th- order transfer function. With a 400MHz sampling rate and 64× OSR, this modulator achieved a maximum 56dB SNDR and 62dB dynamic range in a 3.1MHz bandwidth.

Extra loop delay in a continuous-time modulator can cause a stability problem, especially when the modulator uses a high-order single-loop architecture and operates at a high sampling rate. This paper investigates the impact of extra loop delay on the performance of high-order (single-loop) modulators. A solution to compensate this delay and thereby optimize performance is proposed in this paper. The circuit architecture for this solution is also presented to facilitate a practical realization.

A low-cost, high-efficiency, compact architecture of a PWM (pulse-width-modulation) drive fan controller is designed for use in an embedded multicomputer system with an integrated hierarchical thermal management scheme. This pure digital design yields lower cost and higher conventional linear drive fan providing the functionality and advantages of PWM drive fan controllers. The implementation and system integration of this circuit is also described in this paper.

A Zener-diode-activated electrostatic discharge (ESD) protection circuit is implemented in a 0.5 /spl mu/m CMOS process. This ESD circuit uses a substrate p-n-p transistor with its base connected to a Zener diode to discharge the electrostatic energy. The Zener diode implementation utilizes a silicide block capability to avoid short circuits in the active area. Its performance has been tested by the human body model and a high-speed ESD test. Its latchup-free characteristic makes it an ideal circuit for ESD protection of I/O pads, ESD clamping between power rails, poly-antenna effect protection, and overshoot attenuation.

A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to minimize the offset of the common-mode voltage. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. Simulation and testing results show the superior performance of this circuit. It is proven to be an ideal common-mode feedback circuit for systems which require an accurate and stable common-mode voltage. This circuit has been implemented in a continuous-time switched-current /spl Sigma//spl Delta/ modulator with a 2 /spl mu/m CMOS process. With a 50 MHz clock, the modulator has achieved a 60 dB dynamic range in a 1 MHz bandwidth.

A high-speed fully differential current switch is presented. The clock-feedthrough effect is reduced by Swing-Reduced Drivers (SRDs) and neutralized by dummy transistors. With the use of SRDs, less charges are required to be transferred to/from the gates of the switching transistors, and hence, the switching speed can be increased without significant output error. The SRDs also reduce the possible large current spikes on the outputs of the current switch. Analysis shows this current switch is ideal for high-speed current-mode signal processing. A continuous-time switched-current /spl Sigma//spl Delta/ modulator using these current switches has been implemented in a 2 /spl mu/m CMOS process and achieved a 50 dB dynamic range with a 50 MHz clock.

This paper discusses circuit design problems when implementing low-pass CMOS continuous-time switched-current Ca modulators for high-speed operation or wide-bandwidth conversion. These problems cause difficulties when certain high-performance architectures are intended to be used for improving performance, such as multi-bit quantizer, cascade structure, high-order single loop structure, and parallelism. These problems arise mainly as a result of an uncertain transfer function, an extra loop delay, and/or mismatching among integrator capacitors of the modulator. These problems will be discussed to explore the limitation when more advanced architectures are applied.

A high-speed on-chip temperature sensor is implemented in a 0.6µm CMOS process for the purpose of quickly detecting circuit overheating. By using a high-speed differential current switch and a switched-current proportional-to-absolute-temperature PTAT (ΔVBE) generator, this temperature sensor is able to operate at high speed without suffering from switching noise or input offset problems. A sensing amplifier with chopped output stage and a low-offset current mirror minimize the offset at the output stage. Analog-to-Digital conversion is achieved by a low-power continuous-time switched-current ΣΔ modulator with a 10-bit resolution within 0°C to 150° at a 100kHz output rate. Powered by a single 3.3V power supply, this sensor has an active area of 0.11mm2and a power consumption of 2.9mW with a 40MHz clock.

A new approach for implementing a digital decimator for high-speed /spl Sigma//spl Delta/ modulators is presented. With the use of carry-saved adders, this decimator is able to operate at high speeds while maintaining the same throughput. By using systematic modular design, this filter can be easily designed and implemented with any order and any length, which greatly reduces the time and effort for circuit design. A prototype of a fourth-order length-16 digital comb filter has been implemented with a 1.2 /spl mu/m standard CMOS process. With a single 5 V power supply, this filter can operate at a frequency up to 115 MHz. The power consumption is about 35 mW and the active area is 1083/spl times/965 /spl mu/m/sup 2/.

Feed-forward gain compensation schemes can stabilize the loop gains of CMOS continuous-time /spl Sigma//spl Delta/ modulators without introducing extra feedback loops. These methods accurately control the gain of each integrator in the modulator to optimize the modulator's dynamic range. Without internal feedback for the integrators, these modulators can operate at much higher speeds. Two different gain compensation schemes, one with reference current generators and the other with voltage-controlled voltage-to-current converters, are presented. Their circuit design issues and performance limitations are discussed and compared.

An output pad driver which tristates shortly after negation is presented in this paper. It is suitable for single-board computers where different bus controllers respond to different parts of the address map, and thus multiple components may individually drive handshaking signals to communicate with the processor. Since the operation of the pad driver requires only one internal control signal, it provides a simple solution to the targeted problem. Also, high-speed operation is achieved because the pad driver actively negates before tristating. Furthermore, a wide range of capacitive loads is supported because the pad driver senses its output voltage.

A high-speed high-resolution CMOS current comparator is presented. A dynamic gain boosting stage is used to maximize the comparator gain while maintaining acceptable power consumption. A PMOS regenerative amplifier together with a source follower stage is used to reduce the comparison time and increase the resolution. The charge kick-back (feedback) effect is minimized by properly resetting a few internal nodes and by using an input stage. This circuit has been implemented in a 1.2 /spl mu/m CMOS process and achieved 100 nA resolution at a sampling rate up to 110 MHz and 170 nA resolution up to 140 MHz with a single 5 V power supply.

This paper presents an analytical model for on-chip heat dissipation in VLSI design. A chip and its test configuration also are developed to verify modeling results. The model and chip are representative of general IC packages. Our research shows that circuit location on a chip determines its default offset temperature and heat transport properties, which must be considered for accurate prediction of junction temperature and electrothermal analysis. The model yields insights about on-chip heat dissipation, which are very useful for mixed-signal VLSI designs and circuit reliability analysis.

A new architecture of second-order continuous-time switched-current /spl Sigma//spl Delta/ modulator is presented. A reference current generator is used in the second stage to solve the scaling problem. A novel current switch is designed to minimize the clock feedthrough problem and increase the operating speed. With a 50 MHz sampling rate, it has achieved 50 dB dynamic range (8-bit) at 1 MHz. This modulator has been fabricated in a 2 /spl mu/m CMOS process with an active area of 0.37 mm/sup 2/. The power dissipation is 15 mW.

Excess loop delay in a continuous-time switched-current ΣΔ modulator causes a stability problem and degrades the modulator's dynamic range. This paper presents a simple and effective way to reduce the loop delay and improve the modulator's performance. The loop delay of the ADC is reduced by feeding the “predicted next state” to the comparator. With reduced loop delay, a larger loop gain is allowed without a stability problem, and hence, the dynamic range of the ADC is improved. A new circuit architecture to realize a second-order modulator with this method is also presented. From the simulation result, the new architecture shows a 6–10 dB improvement in dynamic range for a second-order ΣΔ modulator.