A 50 dB-Ω transimpedance amplifier (TIA) with a bandwidth greater than 110 GHz has been demonstrated using InP HBT technology. The wide-band amplifier with a cutoff frequency > 110 GHz was designed and fabricated in HRL Laboratories' G4 0.25 μm InP HBT IC technology. The amplifier operates at -4.0 V with a current draw of 76 mA for a power consumption of 304 mW. The basic Cherry-Hooper gain cell is used with a single-ended input and a differential output buffer stage.

The high operating power density and aggressively scaled geometries associated with 400+GHz InP-Based DHBTs present a new challenge in device design and thermal management. In order to assess the effects of self-heating on the RF performance, S-parameters of six InP DHBTs with varying emitter dimensions were measured over a 75°C ambient temperature range. An 8–10% increase in peak fT is observed as the temperature is reduced. Data analysis indicates that reductions in the base and collector transit times and the base–emitter charging times are responsible for the peak fT improvement. The calculated electron velocities exceed 6×107cm/s, indicating velocity overshoot plays a critical role in the reduction of the transit times. When emitter scaling are considered, the total transit time variation is directly correlated to the rise in junction temperature. Using previously measured thermal resistance values, a 77–116°C minimum junction temperature rise is estimated from self-heating. Therefore, the 8–10% increase in peak fT is a reasonable estimate of the performance to be recovered by minimizing self-heating. Improved intra-device thermal management through device design is an important supplement to geometry scaling as a means to enhance device performance.

Recent attempts to achieve 400 GHz or higher f(T) and f(MAX) with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tau(C) to be minimized without incurring a large total C-BC increase, and hence, a net improvement in f(T) and f(MAX) is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in C-BC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on f(T) and f(MAX). Parasitic resistances and high background doping limit the f(T) improvement, but the C-BC reduction is sufficient to demonstrate a 30% increase in f(MAX). Results indicate that further improvements in f(T) and f(MAX) using the SIBS concept will be possible.

The selectively implanted buried subcollector (SIBS) is a method to decouple the intrinsic and extrinsic C-BC of InP-based double-heterojunction bipolar transistors (DHBTs). Similar to the selectively implanted collector (SIC) used in Si-based bipolar junction transistors (BJTs) and HBTs, ion implantation is used to create a N+ region in the collector directly under the emitter. By moving the subcollector boundary closer to the BC junction, SIBS allows the intrinsic collector to be thin, reducing tau(C), while simultaneously allowing the extrinsic collector to be thick, reducing C-BC. For a 0.35 x 6 mum(2) emitter InP-based, DHBT with a SIBS, 6 fF total C-BC and > 6 V BVCBO were obtained with a 110-nm intrinsic collector thickness. A maximum f(T) of 252 GHz and f(MAX) of 283 GHz were obtained at a V-CE of 1.6 V and I-C of 7.52 mA. Despite ion implantation and materials regrowth during device fabrication, a base and collector current ideality factor of similar to2.0 and similar to1.4, respectively, at an I-C of 100 muA, and a peak dc beta of 36 were measured.

We have demonstrated InP/InGaAs/InP MBE-grown DHBTs fabricated with patterned sub-collector by elevated temperature 200°C N+ implant and subsequent device material over growth. Ft/Fmax>250GHz/300GHz were obtained on DHBTs with 0.35μm×6μm emitters from this process. Ring oscillators fabricated with this process showed good uniformity with 82% of yield on wafers and an average gate delay of 8ps. Difference of surface morphology on re-grown DHBT layers over elevated temperature implanted and room temperature 22°C implanted sub-collector was observed.

Recent developments in highly scaled SiGe and InP IC technologies have yielded devices with f(T) and f(max) figures-of-merit well beyond 300GHz, bringing with them the potential to operate circuits of considerable complexity at clock rates exceeding 100GHz. An initial emphasis upon digital applications helps to put the technologies on a roadmap where further development can be fueled to open the door to other mixed-signal possibilities. Designing circuits at these frequencies requires a balance of thermal and electromagnetic concerns along with the traditional IC design issues, but measured results are demonstrating that these concerns are manageable.

Direct digital synthesis of signals in the hundreds of megahertz can lead to simpler, smaller transceivers, free of images and LO feedthrough that plague systems requiring analog upconversion. We present a 3-bit, 2 GS/s, /spl Delta//spl Sigma/-modulated DAC in InP HBT technology. The DAC is linearized using bandpass mismatch shaping. The mismatch shaper uses seven tunable 1.5-bit discrete-time bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. These /spl Delta//spl Sigma/ modulators operate in the analog domain to decrease system complexity and power consumption. The mismatch-shaped DAC can generate narrowband signals between 250-750 MHz with >68 dB SNR in a 1-MHz bw, >74-dB SFDR, and <-80-dBc intermodulation distortion with an 8.1-W power consumption.

A packaged 43-Gb/s clock and data recovery circuit with 1:2 demux in a 1/spl mu/m InP SHBT technology is reported. A half-rate phase/frequency detector incorporating a four-phase LC-ring oscillator is implemented in the phase and frequency locked loop thus eliminating an external reference clock as a frequency acquisition aid. Measured pull-in and hold-in ranges are 0.9 GHz and 1.1 GHz, respectively, with a peak-to-peak clock jitter of 4.5 ps at 43-Gb/s input data rate.

We present the results of an InP HBT device development process. We have developed a new HBT device fabrication approach that represents a major departure from traditional compound semiconductor manufacturing techniques. The new generation of deep submicron InP-based HBTs presented here uses an ion implanted subcollector and offers significantly improved performance, integration, and device reliability over traditional mesa isolated devices. We have fabricated both SHBT and DHBT selectively ion implanted subcollector InP HBT devices with Ft’s greater than 260GHz.

We demonstrate molecular-beam epitaxy (MBE)-grown heterojunction bipolar transistors (HBTs) on InP substrates with a patterned implant n+ subcollector below the epitaxial layers. Device layers grown on implanted/annealed substrates were of similar quality to those on virgin InP. Maximum f/sub t/ and f/sub max/ of 240 and 310 GHz were obtained. We present the process flow, details of the ion implantation, layer characterization, and device results.

We demonstrate molecular-beam epitaxy (MBE)-grown heterojunction bipolar transistors (HBTs) on InP substrates with a patterned implant n+ subcollector below the epitaxial layers. Device layers grown on implanted/annealed substrates were of similar quality to those on virgin InP. Maximum f/sub t/ and f/sub max/ of 240 and 310 GHz were obtained. We present the process flow, details of the ion implantation, layer characterization, and device results.

We present the results. of measurements of thermal resistivity of the heterojunction bipolar transistor (HBT) devices, utilizing selective ion implantation to define the subcollector. This new device fabrication technique resulted in high-speed HBT devices with substantially reduced thermal resistivity, compared to devices utilizing. the conventional fabrication approach which includes mesa isolation for pattern definition. The measurements were taken on-full-thickness 3" InP wafers at T-amb from 30 degreesC to 180 degreesC and two separate emitter current densities. We present data on three device epitaxial structures, with identical device layouts and discuss the relationship of V-be to temperature,at these elevated power and temperature levels.

This paper summarizes our recent work on high-speed photonic analog-to-digital conversion (A/D) technologies, where picosecond pulses generated by a 10 GHz mode-locked laser source were used to accomplish low-jitter photonic sampling. In addition, we describe our progress in the generation of 40 GHz wavelength-coded pulses for time-interleaved A/D, and the demonstration of photonic bandpass (at 1.6 GHz) Δ-∑ quantizers clocked at 10 GHz.

A 3b /spl Delta//spl Sigma/-modulated mismatch-shaped DAC is presented. The mismatch shaper uses 7 tunable 1.5b switched-capacitor bandpass /spl Delta//spl Sigma/ modulators to dynamically route the digital signals to the DACs. The DAC can generate narrowband signals from 250 to 750MHz with /spl ges/68dB SNR, /spl ges/74dB SFDR, and -80dBc intermodulation distortion.

Operation of a static, current mode logic (CML) frequency divider to clock frequencies exceeding 150GHz is reported. The divide-by-8 circuit described here has been realized in a highly scaled 0.4/spl mu/m InP/InGaAs/InP DHBT technology, dissipates only 45mW per latch, and achieves this using purely resistive loads. Thermal limitations in device performance are observed to play a key role, demonstrating the need for aggressive heat management in high speed technologies. On a full thickness wafer in a 27/spl deg/C ambient, the maximum operating frequency of the divider was 143.6GHz; this range extended to 151.2GHz when an air flow at -30/spl deg/C was established across the wafer.

Bandpass modulators sampling at high IFs (/spl sim/200 MHz) allows direct sampling of the RF signal, reducing analog hardware, and makes it easier to realize completely software programmable receivers. This paper presents the circuit design of and test results from a continuous time tunable IF sampling 4/sup th/ order bandpass delta-sigma modulator implemented in InP HBT IC technology for use in a multi-mode digital receiver application. The bandpass /spl Delta//spl Sigma/ modulator is fabricated in AlInAs/GaInAs heterojunction bipolar technology with a peak unity current gain cutoff frequency (f/sub T/) of 130 GHz and a maximum frequency of oscillation (f/sub MAX/) of 130 GHz. The 4/sup th/ order bandpass /spl Delta//spl Sigma/ modulator consists of two bandpass resonators that can be tuned to optimize both wideband and narrowband operation. The IF is tunable from 140 MHz to 210 MHz in this /spl Delta//spl Sigma/ modulator for use in multiple platform applications. Operating from /spl plusmn/5 V power supplies, the fabricated 4/sup th/ order /spl Delta//spl Sigma/ modulator sampling at 4 GSPS demonstrates stable behavior and achieves a signal to (noise+distortion) ratio (SNDR) of 78 dB @ 1 MHz BW and 50 dB @ 60 MHz BW. The average SNDR performance measured on over 250 parts is 72.5 dB @ 1 MHz BW and 47.7 dB @ 60 MHz BW.

Thermal management is of critical concern in high performance InP-based HBTs, because enhancements in RF performance are typically obtained with increased current density and aggressive device scaling. The resulting increase in junction temperature can degrade carrier transport and negatively affect overall device reliability. This paper reports an investigation of thermal resistance in InP-based HBTs with various vertical and lateral designs. Three-dimensional simulations and experimental results illustrate that significant differences in thermal resistance can arise with relatively small changes in device structure.