An optimized 4-way stress integration on partially-depleted SOI (PD-SOI) CMOS is presented. An embedded-SiGe process and a compressive-stressed liner film are used to induce compressive strain in the PMOS (PMOS "stressors"). A stress memorization process and a tensile-stressed liner film are used to induce tensile strain in the NMOS (NMOS "stressors"). With optimization, the different stress techniques are highly compatible and additive to each other, improving PMOS and NMOS saturation drive current by 53% and 32%, respectively. This improvement results in 40% higher product speed. To demonstrate the extendibility for future transistor nodes the stress improvements were increased further resulting in record PMOS performance of IDSAT=860muA/mum at 200nA IOFF (self-heating corrected) and 1V. The stress techniques are proven in AMD's 90nm manufacturing processes, and have been scaled for use in 65nm manufacturing

For the first time, tensile and compressively stressed nitride contact liners have been simultaneously incorporated into a high performance CMOS flow. This dual stress liner (DSL) approach results in NFET/PFET effective drive current enhancement of 15%/32% and saturated drive current enhancement of 11%/20%. Significant hole mobility enhancement of 60% is achieved without using SiGe. Inverter ring oscillator delay is reduced by 24% with DSL. Overall yield for the DSL process is comparable to that of a similar technology without DSL. Single and multi-core SOI microprocessors are being manufactured using the DSL process in multiple, high-volume fabrication facilities.

Table 1: SOISTA-determined initial-condition delays versus circuit simultaion delays. SOISTA detailed SPICE steady-state Rise Fall short path long path max min max min rise fall rise fall Table 2: SOISTA-determined detailed steady-state delays versus circuit simulation delays. determined by circuit simulation (after more than 50,000 cycles of simulation) and the SOISTA-determined detailed steady-state delays. In all cases, the SOISTA-determined delays bound the SPICE delays. One should also notice the considerable reduction in uncertainty between the initial-condition and detailed steady-state delays, as the component of this uncertainty due to body voltage variation is noticeably reduced. (The remaining uncertainty is due primarily to delay-path variation and loading uncertainty.) 6 Conclusions and future work In this paper, we have presented a circuit-focussed model of the oating-body potential of PD-SOI FETs. This model allows one to determine the body voltage and its associated uncertainty, depending on knowledge of the switching activity of the FETs in question. Four types of estimation are possible depending on switching assumptions and the amount of information known about the logical and temporal environment of the circuit under analysis. We have incorporated this model into a prototype transistor-level static timing analysis engine to demonstrate the impact reduced body-voltage uncertainty can have on performance evaluation. We nd that the body-voltage uncertainty can be signiicantly reduced with fairly conservative assumptions about switching behavior. Future work will include incorporating these body voltage estimates into transistor-level static noise analysis. In addition, we intend to consider design techniques whereby a normally inactive block could be periodically stimulated to keep it \primed" so that when it is eventually exercised, it has more tightly predictable body voltage variation. This is similar to some of the circuit techniques which attempt to force discharge of the body during \non-critical" periods of circuit operation (e.g. precharge in dynamic logic) to reduce parasitic bipolar leakage. In many ways, this could also be viewed as analogous to DRAM refresh. More work will be required to determine the necessary frequency and nature of this pattern. noise analysis for deep-submicron digital integrated circuits.sign for suppression of gate-induced drain leakage in LDD MOS-FETs using a quasi-two-dimensional analytical model. input waveforms shown in the inset of Figure 6(a), which sensitizes the critical path of this circuit, the carry chain. The \A" waveform is applied to each A input and the \B" waveform is applied to each B input. The \C" waveform is applied to the Cin …

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V/sub th/ implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t/sub si/ examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity.< >

The scaling relationships among three fundamental quantities of deep-submicron MOSFET's, i.e., effective channel length L(eff), device speed g(m)/WCox, and drain-induced barrier lowering (DIBL) delta V-t/delta V-ds, are investigated using both device measurements and numerical simulations. It is found that these relationships can be expressed in power-law forms with excellent statistical significance for both experimental and simulation data samples. The dependence of these scaling relationships on two sets of device parameters is also investigated experimentally and confirmed by numerical simulations. These two sets of parameters are: 1) channel parameters-gate oxide thickness tot, threshold voltage V-t, and channel doping profile; and 2) source/drain parameters-junction depth x(j), parasitic resistance R(sd), and junction abruptness (e.g., ''halo'' doping structure). In the deep-submicron regime with L(eff) from 0.5 mu m down to sub-0.1 mu m, it is found that certain relationships among the three fundamental quantities are insensitive or ''universal'' with respect to particular subsets of device parameters. The relationship between g(m)/WCox and delta V-t/delta V-ds, with L(eff) as an implicit variable is found to be insensitive to t(ox), V-t, and channel doping profile within their respective experimental ranges. The trade-off between device performance (represented by g(m)/WCox) and short channel effect (represented by delta V-t/delta V-ds) is dominated by source/drain parameters x(j), R(sd) and junction abruptness, rather than channel parameters t(ox), V-t and channel doping profile. Also, the power coefficient relating delta V-t/delta V-ds to L(eff) is found to be insensitive to t(ox), V-t, and channel doping profile.

Field-effect transistors (FETs) in conventional electronic circuits are in contact with the high-thermal-conductivity substrate. In contrast, FETs in novel silicon-on-insulator (SOI) circuits are separated from the substrate by a thermally resistive silicon-dioxide layer The layer improves the electrical performance of SOI circuits. But it impedes conduction cooling of transistors and interconnects, degrading circuit reliability, This work develops a technique for measuring the channel temperature of SOI FETs. Data agree well with the predictions of an analytical thermal model. The channel and interconnect temperatures depend strongly on the device and silicon-dioxide layer thicknesses and the channel-interconnect separation. This research facilitates the thermal design of SOI FETs to improve circuit figures of merit, e.g., the median time to failure (MTF) of FET-interconnect contacts.

The intrinsic DC device performance tradeoff between current drive and short-channel effect is explored experimentally in a wide range of bulk and SOI devices. For the range of devices studied, the intrinsic performance tradeoff is improved primarily by the junction technology (e.g. use of "halo" structure) in bulk devices and the silicon film thickness or mode of operation (fully or partially-depleted) in SOI. Comparing bulk and SOI devices, fully-depleted devices behave similarly to bulk devices, while partially-depleted devices are more complicated due to the floating-body effects.<>

The optimization of device series resistance in ultra-thin film SOI devices is studied through 2-D simulations and process experiments. To achieve low series resistance, very thin silicides that do not fully consume the SOI film are needed. A novel cobalt salicidation technology using titanium/cobalt laminates is used to demonstrate sub-0.2 /spl mu/m, thin-film SOI devices with excellent performance and very low device series resistance.< >

Short-channel effects in deep-submicrometer SOI MOSFET's are explored over a wide range of device parameters using two-dimensional numerical simulations. To obtain reduced short-channel effects in SOI over bulk technologies, the silicon film thickness must be considerably smaller than the bulk junction depth because of an additional charge-sharing phenomenon through the SOI buried oxide. The optimal design space, considering nominal and short-channel threshold voltage, shows ample design options for both fully and partially depleted devices, however, manufacturing considerations in the 0.1 mum regime may favor partially depleted devices.

SOI NMOS devices incorporating the constant dose design concept were fabricated. The devices had a gate oxide of 8 nm, a buried oxide of 380 nm, and a silicon film thickness (t/sub Si/) that ranged between 42 nm to 53 nm. All measurements were taken on long channel (L/sub eff/>2 /spl mu/m) devices. The devices implanted with the lowest energy of 20 keV are less sensitive to t/sub Si/ variations than those with the higher implant energy conditions. For comparison, the threshold voltage (V/sub T/) calculated from the analytical model of Lim et al. (1983) is also shown for the constant substrate dopings of 3/spl times/10/sup 17/ cm/sup -3/ and 4/spl times/10/sup 17/ cm/sup -3/. The V/sub T/ sensitivity to t/sub Si/ variations was reduced considerably by using the constant dose design concept.

Thermal conduction in amorphous dielectric layers affects the performance and reliability of electronic circuits. This work analyzes the influence of boundary scattering on the effective thermal conductivity for conduction normal to amorphous silicon dioxide layers, k(n,eff). At 10 K, the predictions agree well with previously reported data for deposited layers, which show a strong reduction of k(n,eff) compared to the bulk conductivity, k(bulk). A steady-state technique measures k(n,eff) near room temperature of silicon dioxide layers fabricated using oxygen-ion implantation (SIMOX). The predictions and the SIMOX data, which agree closely with k(bulk), show that boundary scattering is not important at room temperature. Lower than bulk conductivities of silicon dioxide layers measured elsewhere near room temperature must be caused by interfacial layers or differences in microstructure or stoichiometry.

Channel lengths are continually scaled to smaller dimensions to improve performance and packing density. In recent years this has led to demonstrations of MOSFETs with effective channel length of 0.1 /spl mu/m and below. The key technology challenges at these linewidths include the lithography to reproducibly achieve fine dimensions, source and drain engineering to reduce device parasitics, and channel engineering to control short-channel effects. In this work, we demonstrate a high-performance NMOS technology that utilizes X-ray lithography to achieve channel lengths below 0.1 /spl mu/m; a novel cobalt salicidation (CoSi/sub 2/) technique using a titanium/cobalt laminate to achieve very low parasitic source/drain resistance; and shallow junctions and an optimized super-steep retrograde (SSR) channel profile to achieve very high transconductance devices with excellent control of short-channel effects.<>

Fully-depleted Silicon-On-Insulator (SOI) MOSFETs are a strong potential candidate for future ULSI CMOS applications. In order to evaluate the merits of these devices an accurate model of the output characteristics applicable to sub-half micron channel lengths is needed. Previous work on modeling the I-V (current-voltage) characteristics of thin-film SOI MOSFETs has mainly been based on inaccurate velocity-field relation for carriers in the channel region. Moreover, in most models, conductance and capacitances show discontinuities at the transition points from subthreshold to saturation to linear regions. In this paper we report a physically based continuous analytical model for SOI MOSFETs that is represented by a single drain current equation valid in all regions of device operation ofinterest

Recent studies have shown that high performance 0.1 μm complementary metal–oxide semiconductor (CMOS) can be achieved with proper channel and source/drain engineering. Specifically, retrograde channel doping and shallow source/drain junctions with counterdoping implant (halo) allow the threshold voltage to be kept low while maintaining acceptable short-channel behavior. These studies have certainly demonstrated the feasibility of CMOS technology scaled down to 0.1 μm from a device design point-of-view. However, the main challenge to the lithography technology is to fabricate 0.1 μm metal-oxide-semiconductor field-effect transistor (MOSFET) devices with high yield and high throughput, as required in manufacturing. X-ray lithography is a technology that can potentially meet this challenge. This work shows the results of integrating a low cost x-ray technology with standard IC processing to fabricate high performance 100 nm and even sub-100 nm MOSFETs.

A simple methodology to accurately extract constant temperature model parameters from static measurements of fully-depleted SOI MOSFET current-voltage characteristics is demonstrated. Self-heating is included in an existing physically-based, short-channel bulk MOSFET model, PCIM, by allowing the temperature to change linearly with power dissipation at each bias point. Only a simple modification of the channel bulk charge in PCIM is necessary to adapt it for SOI. The temperature dependence of the physical parameters (mobility, flatband voltage, and saturation velocity) are also fitted and included in the model. Excellent fit to experimental fully-depleted SOI data is shown over a large range of bias conditions and channel lengths. Once the static SOI data is fitted, the constant temperature model parameters appropriate for circuit simulation are easily extracted.< >

The standard bulk MOSFET definition for effective electric field is modified for SOI devices to account for nonzero electric field at the back oxide interface. The effective channel mobility in fully-depleted n-channel SOI MOSFET's is shown to be independent of applied back-gate bias when the modified E(eff) definition is used. The effective channel mobility as a function of E(eff) is also shown to be independent of film thickness for fully-depleted devices.

The authors point out that the reliability and performance of electronic circuits are influenced by heat conduction in low-pressure chemical-vapor-deposited (LPCVD) silicon dioxide layers. Here, the effective thermal conductivity k/sub eff/ for conduction normal to films of LPCVD silicon dioxide layers as a function of annealing temperature, as well as for films of thermal and SIMOX oxides, is measured. The LPCVD oxide thermal conductivity increases by 23% due to annealing at 1150 degrees C. The conductivities k/sub eff/ of LPCVD layers of thicknesses between 0.03 and 0.7 mu m are higher than those reported previously for CVD layers, and vary between 50% and 90% of the conductivities of bulk fused silicon dioxide. The values of SIMOX and thermal oxide layers are within the experimental error of the values for bulk fused silicon dioxide.<>

Due to reported advantages over bulk silicon, thin-film SOI has developed the potential of becoming a mainstream digital technology. In order to accurately model SOI device operation, it is necessary to understand further the channel electron mobility behavior. Some work has been done in characterising the electron mobility in SOI devices and an enhanced mobility effect has been reported by several authors for fully-depleted devices. In these works, the mobility was found to increase for thinner films and this mobility enhancement has been attributed to a decreased vertical electric field in the channel. For the same gate drive, (Vgs-Vth), the thinner fully-depleted SOI device has a reduced transverse field and thus a higher mobility. This work examines the effective mobility (μeff ) as a function of a transverse effective electric field (Eeff) rather than gate voltage or gate drive

Thin-film, fully-depleted silicon-on-insulator (SOI) MOSFETs are currently of great interest due to potentially improved isolation, reduced subthreshold slope, and reduced parasitic capacitances as compared to bulk silicon technology. In addition, for scaling devices into the deep-submicrometer region, SOI offers unique options for the reduction of short-channel effects. Previous work has shown that scaling silicon film thickness and buried oxide thickness are important in the reduction of SOI short-channel effects. However, to fully exploit these options in SOI, a careful examination of the design tradeoffs is necessary. In this paper, short-channel effects in SOI are examined in comparison to conventional bulk devices for scaling into the deep-submicrometer region