The applications of broad spectral photodetectors in the fields of biological imaging and environmental remote sensing have received considerable attention in the past decades. However, the specific photodetectivity representing the lowest optical signal that can be detected by a photodetector remains unsatisfactory. Here. we reported the unprecedent enhancement of specific photodetectivity of broad spectral photodiodes based on the heterojunction of p-Si/polyvinyl pyrrolidone (PVP)-modified perovskite by introducing fullerene (C60) as the hole blocking layer (HBL). The results showed that, by inserting a C60 HBL between the PVP-perovskite and the top electrode, the dark current is significantly reduced and strongly dependent on C60 thickness. The dark current reaches a minimum at C60 thickness of 10 nm, which is only roughly one-thirtieth of that without the C60 layer. At the optimized C60 thickness, the specific photodetectivity is enhanced about an order of magnitude due to significantly reduced dark current, while the photoresponsivity ( ${R}$ ) only slightly reduced.

The hydroxy amino acids have its unique effects in the biotechnology and molecular biology, and all sorts of synthetic hydroxy amino acids have also been developed. The hydroxy amino acids have been proved to be valuable for antifungal, antibacterial, antiviral and anticancer properties and known as a constituent of pharmaceutical intermediates. In addition to these fundamental researches, the hydroxy amino acids are applied widely to the synthesis of chiral drugs, such as (2S, 3R, 4S)-4-hydroxyisoleucine (4-HIL) is proved to be worthy in medical treatment, cis-4-hydroxy-L-proline (C4LHyp) and trans-4-hydroxy-L-proline (T4LHyp) are applied to build the chiral intermediates in pharmaceutical synthesis. Through comparisons chemical synthesis with biological catalysis to form hydroxy amino acids, enantioselective biocatalysts will undoubtedly be used in the synthesis of chiral pharmaceuticals. Mononuclear non-heme Fe(II)/α-ketoglutarate-dependent dioxygenases (Fe/αKGDs) that use an Fe(IV) complex intermediate to active diverse oxidative transformations with key biological roles. Studies identifying the important intermediates in catalysis and the proposed mechanisms are explained. In summary, we describe the physiological properties and synthesis regarding hydroxy amino acids, particularly 4-HIL and hydroxyproline. And the proposed catalysis mechanisms of Fe/αKGDs are also explained, while we also discussed the applications of hydroxy amino acids in fundamental research and industrial.

Based on the assumption of Gaussian energy distributions of the lowest unoccupied molecular orbital (LUMO) and the highest occupied molecular orbital (HOMO), analytical expressions of generalized Einstein relation in chemically doped organic semiconductor are developed, by approximation of Coulomb traps with a rectangle potential well. Numerical calculations show that traditional Einstein relations do not hold for chemically doped organic semiconductors. Similar to physical doping, the dependence of diffusion coefficient to mobility D/μ ratio on the carrier concentration has a maximum. An essential difference between chemical doping and physical doping is that, the D/μ ratio in chemically doped organic semiconductors depends not only on carrier concentration and doping concentration, but also on the applied electric field.

Under the assumption of Gaussian energy distributions of the lowest unoccupied molecular orbital (LUMO) and the highest occupied molecular orbital (HOMO), analytical expressions of generalized Einstein relation for electron and hole transport in doped organic semiconductor thin films are developed. Numerical calculations show that, although traditional Einstein relation still holds for low carrier concentrations, that is, the diffusion-coefficient-to-mobility ratio in units of kBT/q, with kB the Boltzmann’s constant, T the temperature and q the elementary charge, equals 1. But when the electron (hole) concentration is high, the diffusion-coefficient-to-mobility ratio for electrons (holes) changes strongly with the electron (hole) concentration, the doping level, the mean energy of LUMOs (HOMOs) of the dopant ELd (EHd) and the host EL (EH), as well as their variances. Dopants with ELdEH) affect the diffusion-coefficient-to-mobility ratio mainly in the range of low and middle carrier concentrations, while those with ELd>EL (EHd

It has been reported (Kuang et al., 1997; Lu et al., 1997) that SOI passgate circuits suffer history effects and adverse initial-cycle parasitic bipolar currents, which cause difficulties in circuit timing and limit direct design reuse from original bulk circuits. SOI device body history can also induce transfer characteristics mismatch in dual-railed static or dynamic CMOS circuits, resulting in speed degradation or functional failures. This paper describes an efficient technique to alleviate initial-cycle bipolar currents while retaining the low-V/sub t/ floating body feature when the SOI devices concerned are on. We also present a dynamic body discharge technique to eliminate the mismatch problems in cross-coupled SOI CMOS topologies, for use in a variety of circuit families such as cascade voltage switch logic, latch-type sense amplifiers and analog operational amplifiers.

Table 1: SOISTA-determined initial-condition delays versus circuit simultaion delays. SOISTA detailed SPICE steady-state Rise Fall short path long path max min max min rise fall rise fall Table 2: SOISTA-determined detailed steady-state delays versus circuit simulation delays. determined by circuit simulation (after more than 50,000 cycles of simulation) and the SOISTA-determined detailed steady-state delays. In all cases, the SOISTA-determined delays bound the SPICE delays. One should also notice the considerable reduction in uncertainty between the initial-condition and detailed steady-state delays, as the component of this uncertainty due to body voltage variation is noticeably reduced. (The remaining uncertainty is due primarily to delay-path variation and loading uncertainty.) 6 Conclusions and future work In this paper, we have presented a circuit-focussed model of the oating-body potential of PD-SOI FETs. This model allows one to determine the body voltage and its associated uncertainty, depending on knowledge of the switching activity of the FETs in question. Four types of estimation are possible depending on switching assumptions and the amount of information known about the logical and temporal environment of the circuit under analysis. We have incorporated this model into a prototype transistor-level static timing analysis engine to demonstrate the impact reduced body-voltage uncertainty can have on performance evaluation. We nd that the body-voltage uncertainty can be signiicantly reduced with fairly conservative assumptions about switching behavior. Future work will include incorporating these body voltage estimates into transistor-level static noise analysis. In addition, we intend to consider design techniques whereby a normally inactive block could be periodically stimulated to keep it \primed" so that when it is eventually exercised, it has more tightly predictable body voltage variation. This is similar to some of the circuit techniques which attempt to force discharge of the body during \non-critical" periods of circuit operation (e.g. precharge in dynamic logic) to reduce parasitic bipolar leakage. In many ways, this could also be viewed as analogous to DRAM refresh. More work will be required to determine the necessary frequency and nature of this pattern. noise analysis for deep-submicron digital integrated circuits.sign for suppression of gate-induced drain leakage in LDD MOS-FETs using a quasi-two-dimensional analytical model. input waveforms shown in the inset of Figure 6(a), which sensitizes the critical path of this circuit, the carry chain. The \A" waveform is applied to each A input and the \B" waveform is applied to each B input. The \C" waveform is applied to the Cin …

This paper presents a detailed study on the impact of the floating body in a partially depleted (PD) SOI MOSFET on a multi-level voltage-switch current-steering type circuit using the dynamic CVSL XOR circuit as an example. It is shown that because of the cascading, differential input configuration, symmetry, and crisscross drain connections in the circuit topology, both normal-mode and inverse-mode parasitic bipolar effect (with parasitic bipolar current flowing from the source to the drain) will be present in every cycle when the clock changes from the precharge phase to the evaluation phase. The resulting impact on the circuit operation, stability and functionality is studied. The normal-mode parasitic bipolar effect is shown to lead potentially to an erroneous logic state. The history dependency (hysteresis) and pattern dependency of the parasitic bipolar effect are discussed.

This paper reviews the recent advances of silicon-on-insulator (SOI) technology for complementary metal-oxide-semiconductor (CMOS) very-large-scale-integration memory and logic applications. Static random access memories (SRAMs), dynamic random access memories (DRAMs), and digital CMOS logic circuits are considered. Particular emphases are placed on the design issues and advantages resulting from the unique SOI device structure. The impact of floating-body in partially depleted devices on the circuit operation, stability, and functionality are addressed. The use of smart-body contact to improve the power and delay performance is discussed, as are global design issues.

Rapid fluctuations of power supply values, or switching noise, can have a significant effect on VLSI circuit speed. This is shown by comparing circuit simulations with measurements of the critical path delay of a self-resetting SRAM. It is shown that including the measured high frequency noise in the circuit simulation leads to very accurate prediction of circuit speed.

Strain space plasticity theory has been advocated by a number of researchers as a viable alternative to its stress space counterpart. However, there appears to be a certain level of uncertainty about the equivalence of stress- and strain-based plasticity theories. This paper attempts to clarify some issues raised by Casey and Naghdi [2] concerning the equivalence of these two theories. By providing the alternative conjugate expressions for the loading criteria, it will be shown that the two formulations are indeed equivalent in substance and produce equivalent expressions for the plastic strain rate, provided that the material laws used are identical in both approaches. The use of the strain space formulation in many cases, for example, when dealing with strain-softening materials, is deemed to be convenient and therefore desirable. Nevertheless, it is not essential.The findings in this article exemplify the statement made by Drucker [4]: 'The use of a strain space or a stress space is equally permissible, but may not be equally convenient for one purpose or the other.'

Introduction: The design of fast and robust Cache hit logic was one of the fundamental hurdles overcome to achieve the reported 35OMHz for a S/390 Microprocessor in a O.&n Leff technology’. The 4 way set associative Cache mechanism is shown in Figure 1. It consists of the Cache memory’which holds a subset of the machine instructions and data, the Director), memory which holds a subset of absolute addresses (main memory addresses) corresponding to the Cache’s instructions and data entries, the absolute Translation Lookaside Bufer (TLB) which holds recently translated absolute address entries, and the logical TLB which holds the virtual addresses (internally generated machine addresses) corresponding to absolute TLB’s address entries. The hit logic, which links all these memories together, is used to resolve whether the Cache memory holds the instructions or data requested by the processor each cycle. If the Cache holds the correct entry, the hit logic selects the appropriate entry from 4 possible sets simultaneously read out of the Cache. While most of the processor logic was implemented in static CMOS, performance requirements dictated that the hit logic employ precharge techniques to achieve a single cycle directory lookup and set selection. This in turn caused a number of circuit issues to surface which relate to the proper interfacing of static and precharged logic families. Flexible timing control was incorporated around these interfaces, where races exist, to obtain functional hardware at all process and test comers. Timing Diagram: Figure 2 shows the timing diagram for the logic and memory circuits. The down going edge of the Global Clock triggers both the capture and launch of signals through the logic registers, begins the precharge of the hit logic (Hit L. precharge), and starts the internal decode of addresses in the memory macros. About half way through the cycle, the 7ZB andDirectory memories send their outputs to the conipamtor logic which in turn drives the Anding arid Coritiriuation logic. The hit signal produced by the sum of those actions finally selects one of four possible cache entries driven out to the Cache Output Register. All memory accesses and logic evaluations happen in a single processor cycle. Recharge occurs when circuits are not evaluating. Each functional block in the memory circuits generates its own precharge using a self-resetting scheme2 (SRCMOS). Direcfoq) and T U memories produce a wide enough output pulse, approximately a third of the cycle, to guarantee sufficient overlap between their signals such that bit “Anding” done in XOR circuits, a part of the Directory Comparator, functions reliably. Once the hit logic topples, data stay latched until the next cycle precharge. The single phase clocking scheme described is prone to short path timing problems introduced through the precharge of the hit logic. Clock skew may cause the hit logic to precharge before a latch capturing the hit logic’s state has time to close. Padding prevented this situation from occurring. Strobed Compare Equal Circuit: Figure 4 shows the Directory comparator circuit consisting of a bit by bit XOR followed by a strobed “Anding” plane. The primary complication of this comparator is that it requires a timing circuit to assert the strobe only after the XOR circuits have had a chance to detect a difference between the TLB and directory signals, and if a single bit miscompares, t r ig ger a NOR transistor to pull down dynl. A race condition exists between data arriving and strobe assertion. Activating the strobe too early causes the comparator to functionally fail with a constant signature of a high Compare-Equal while activating the strobe too late adds dead time to the circuit delay. Note also that all precharge circuits, figures 4 & 5, use keeper PFETs, PNl, 2, 3, to manage charge sharing and leakage on dynamic nodes and skewed static inverters (not shown) to remove coupling noise introduced on long signal lines. In Figure 3, E-beam results for the Strobe Compare Equal Circuit were obtained from a test site with visible circuit nodes and precise strobe timing control. The first waveforms show the 200pSec circuit performance from the pulsed input dir-Trising to the output Conipare-Equal rising. To achieve that performance, the second waveforms show that the Strobe is triggered before node dynl is pulled down. The third waveform shows how the overly aggressive Sbobe setting produces a noise glitch, for the miscompare case, which indicates dyn2 is partially discharged through transistors NI, N2, and NSTROBE. A half latch, transistor PNI, recovers the node dyn2 high once transistor NI shuts off. In a real design, such an aggressive strobe setting is not advised since mistracking between the strobe path and the data path can be introduced by long signal wires of varying length, power supply bounce, transistor mistracking, and coupling noise. A strobe timing circuit is shown attached to the comparator in figure 4. The Sfrube signal is developed by “Anding” (ANDI) both the TLB and Directory signals. In this way, the slowest memory is guaranteed to trigger the comparator strobe. An “OR’ (OR1 & 2) of a single bit’s true and complement signals (dir-7’and dir-C, tlb-T and t1b-q determines when a memory launches its data to the comparator, since by design, either the memory’s true or complement signal will go high. The strobe path replicates the comparator path all the way to the XOR input. In an early test version, differences between a memory’s writethrough (i.e. cell is written and read simultaneously) and read access times caused the strobe to trigger before all the comparator data arrived. Each strobe circuit drove two comparators each operating on separate Directory address data. In certain cases, one data field was written-through while lhe other was read. The problem was a fast write-through, in the dedicated timing bits of figure 4, caused a “fast” sfrobe to trigger a comparator, operating on “slow” read data, too early. For the case of a miscompare, the comparator failed with a high Compare-Equal when a low Conpare-Equal was expected. Fortunately, strobing was considered enough of a risk to add a timing control to the strobe circuit. Delaying the strobe cured the functional problem on early test hardware. The final fix included more margin in the strobe and added dedicated strobe circuits to each comparator. A stress mode now tightens the strobe timing during final test to ensure no marginally good hardware escapes. An explanation of how write-though can occur earlier than a read follows: Writing data directly onto a memory’s bit line pair, by pulling down one bit line, can trigger an inverter driving signals out of a sense amplifier without any assistance from the differential amplifier. If the signal swing into the sense amplifier is large enough, which in the write-through case it is, the inverter output goes high once the signal falls below the inverter’s switching threshold. Recall the only function of a sense amplifier in an SRAM is to rapidly amplify a slowly developing bit line difference produced by reading a memory cell. In the strobed comparator, ilexible timing control proved indispensible in fixing an unanticipated failing race. In general, timing control facilities may be incorporated into a design to stress or relax races during testing and burn-in3. Timing control consists of a variable delay element and scannable latches. Scannable latches hold the desired timing mode. They are set before the global clock is asserted. Small variable delay elements are constructed by selectively adding or removing transistor width to an inverter in a timing

High speed level-1 cache applications demand fast single cycle access times and short cycles. Novel circuits that deliver fast access times and self-resetting CMOS (SRCMOS) techniques that deliver fast cycle times are described. Two key elements for fast access times are: fast signal conversion from static CMOS to SRCMOS and fast signal conversion from SRCMOS to static CMOS. These conversions are performed by the input receiver and output driver circuits. A two-stage address decode scheme to minimize gate complexity and a high performance "late select 4-to-1" mux in front of the output drivers are also key elements. A "Sense and Hold Amplifier" (SHA) is used to perform pulse alignment with the asynchronous "late select" signal. The critical redundancy compare path is designed to be as fast as the primary word line decode path in order to minimize any impact on performance. SRCMOS circuitry allows for fast cycle operation without the use of a centrally controlled clocking scheme. Only the receivers are clocked and all subsequent circuits are triggered by pulses generated from preceding stages. Extensive sharing of reset circuitry is employed to minimize the overhead of SRCMOS. The SRAM includes a programmable "Array-Built-In-Self-Test" (ABIST) sub-macro which allows extensive test pattern coverage and access time evaluation at cycle speed.

A 1.5 ns access, 15Kb (4x 128 x 30b) tag SRAM macro capable of cycling at 500 MHz is presented. It is designed for 4-way set-associative cache controller application in a S/390 microprocessor. It features write-through with independent R/W control within each set, and programmable BIST (built-in self-test) capability at cycle speed. The core circuit techniques involved self-resetting CMOS (SRCMOS) for fast access/cycle time, mixed with ''handshaking'' between timing critical blocks to guarantee proper operating margins. A testchip was implemented in a 0.25 mu m (L-eff) CMOS technology with M0 and 3 layers of metal for wiring. Successful hardware operation was achieved over a wide range of supply voltages and temperature.

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on multi-level voltage-switch current-steering type circuit using the dynamic CVSL XOR circuit as an example. It is shown that because of the cascading, differential input configuration, symmetry, and crisscross drain connections in the circuit topology, both normal-mode and inverse-mode parasitic bipolar effect (with parasitic bipolar current flowing from the source to the drain) will be present in every cycle when the clock changes from the precharge phase to the evaluation phase. The resulting impact on the circuit operation, stability and functionality are studied. The normal-mode parasitic bipolar effect is shown to potentially lead to erroneous logic state. The history dependency (hysteresis) and pattern dependency of the parasitic bipolar effect are discussed.

A non-quasi-static (NQS) model accounting for intrinsic carrier propagation delays in both B/E and B/C junctions is implemented in the ASTAP circuit simulator to evaluate the impact of non-quasi-static effects in saturated bipolar circuits. It is shown that while the extra delay introduced by the NQS effects during the turn-on transition is primarily due to the normal mode B/E NQS time constant, the more severe NQS delay in the turn-off transition is caused mainly by the removal of the saturation over-drive charges and the longer inverse mode B/C NQS time constant.<>

As lithographic ground rules are scaled into the deep sub-micron regime in today's VLSI technologies, the proximity of different materials in a given device structure often induces significant mechanical stress. In this paper, we report the observation of the collector current (I(c)) variation induced by the isolation trench in advanced bipolar devices. It is shown that as the trench-intrinsic device separation is pushed into deep sub-micron regime, I(c) decreases in the npn transistors, while it increases in the pnp transistors. We attribute the latter to an in-plane biaxial tensile stress which lowers the electron mobility while enhances the hole mobility in the [001] (vertical) crystal orientation.

An experimental 1-k*16 ECL (emitter coupled logic) dual-port cache RAM block that has a read/write port and an independently accessible read-only port is presented. Multiples of this block can be used to construct a high-performance, large-capacity cache memory. This dual-port memory cell is constructed by adding a differential emitter-coupled sense circuit for the read-only port to the p-n-p-load (or SCR-type) bipolar read/write single-port cell. The p-n-p-load cell is chosen because of its smaller area and better soft-error immunity than other types of bipolar memory cells. The cache block is fabricated using a 0.8- mu m, trench-isolated, double-poly, self-aligned 3.6-V Si-bipolar technology with double metal layers and a W local-interconnection layer.<>

The design of an ECL circuit with AC-coupled self-biased dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array applications is presented. The circuit features an AC-coupled dynamic current source to improve the power-delay of the logic stage (current switch). A self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8- mu m double-poly, self-aligned bipolar technology at a power consumption of 1.0 mW/gate, the circuit offers 1.62* (1.90*) improvement in the speed (load driving capability) of a loaded gate compared with the conventional ECL circuit. >