Raytheon Technologies teamed with Michigan State University and Teledyne Scientific present a zero-IF, mixed-signal, 32-channel millimeter-wave CMOS transceiver design developed under the DARPA/MTO MIDAS program. The architectural choices, design overview, and measured results from two generations of ASIC development are presented. As part of the MIDAS 3D T/R module, element-level digital beamforming provided by this ASIC will allow multiple simultaneous beams over a wide field of regard.

Raytheon Technologies teamed with Michigan State and Teledyne Scientific present a 16-element scalable AESA building block consisting of high efficiency InP HBT power amplifiers (PAs), low noise figure InGaAs HEMT Low Noise Amplifiers (LNA) with integrated T/R switches, a high-density tile interposer containing the TA1 Digital Tile, and wideband antenna to meet the MIDAS TA2 program goals. The architectural, device, and assembly technology choices are presented with Phase 1 results.

A dc-20-GHz multiple-return-to-zero digital-to-analog converter (DAC) is proposed for direct radio frequency synthesis. To minimize frequency-dependent amplitude and phase errors in the output summing node, which can dominate linearity performance at GHz and mm-wave frequencies, a vertically stacked tree (VST) and feed-forward (FF) path are proposed. While the VST minimizes variation in frequency response among the MSB cells, the FF path improves matching between the MSBs and LSBs, providing up to 21-dB improvement in simulated spurious-free dynamic range (SFDR) at 20 GHz. To account for additional errors introduced by process variation, the DAC utilizes per-cell calibration of both amplitude and timing. The DAC is implemented in a 0.13- $\mu \text{m}$ SiGe process with an area of 6.25 mm2 and consumes 1.91 W. After amplitude and timing calibration, >48-dB SFDR and lesser than −46 dBc intermodulation distortion are achieved from dc to 20 GHz.

The push towards mm-wave frequencies has increased the demand for UWB DACs with minimal spurious emissions. At mm-wave, intra-DAC dynamic timing and data errors consume a significant portion of the clock period, degrading SFDR. Previously, NRZ and RZ DACs have been reported with output frequencies up to 27GHz [1–4]. However, their outputs are limited to the first two Nyquist zones, requiring high sample rates which exacerbate dynamic errors. Interleaved DACs allow for synthesis above the first Nyquist zone without increasing the sample rate, although inter-DAC amplitude and timing errors introduce additional spurs at the output that can limit SFDR [5,6]. Alternatively, mixing DACs decouple the sample rate and output frequency, however, they do not deglitch the output, limiting SFDR at high frequency [7]. The multiple return-to-zero (MRZ) architecture mitigates the effects of dynamic errors in the data path, allowing for synthesis up to 9.45GHz with 42dB SFDR [8]. Moreover, the use of R-2R networks achieves binary scaling with the same unit cell current, alleviating switch timing mismatches. Although these techniques improve the intrinsic SFDR of the DAC cells, mismatches in the frequency response of routing interconnects dominate the performance at mm-wave. This is especially critical for the output summing node, which requires an identical amplitude and phase response from each cell to the output. Previously reported DACs used simple structures to combine currents at the output, resulting in large phase and amplitude mismatches. Furthermore, the mm-wave operation of the RZ clock exacerbates the effect of timing errors due to both interconnect and transistor mismatches in the RZ path.

We report a 30 GS/s sample-hold amplifier implemented in a combined InP HBT and Si CMOS heterogeneous integration technology. The high-speed signal path is entirely in InP, but droop in the sampled voltage arising from HBT bias currents is suppressed by an integrated CMOS feedback circuit. Under this closed-loop control, in hold mode, the droop rate of the single-ended outputs is reduced to 20 mV/ns. InP-CMOS interconnect parasitics are isolated from the high-speed signal path by isolation resistors and active bootstrapping. Given an 8 GHz input sampled at 32 GHz, the circuit shows input-referred P1dB and IIP3 of 0.5 dBm and 5.8 dBm, respectively. The total power consumption is 2.7 W and the chip area is 815 × 855 µm2.

Short-Abstract—Recent advances in InP semiconductor device design and high-yield processing have led to the demonstration of transistors with power gain cut-off frequencies (fmax) greater than 1 THz. More importantly, the devices are supported by low-loss interconnects, accurate models and robust design kits. Employing a systematic design methodology that includes significant EM and thermal modeling, we have demonstrated circuit components for transceivers up to 670 GHz and power amplifiers with >100mW of output power operating at 230 GHz. Insertion of these high frequency chips requires additional breakthroughs in packaging, and thermal management. Other applications of the technology would allow the high gain-bandwidth to be traded for high dynamic range and efficiency at mmWave frequencies.

In this work we present recent results on high-speed, multi-Nyquist Digital-to-Analog Converter (DAC) capable of RF signal generation well above 10GHz. The DAC is implemented Teledyne's InP double heterojunction bipolar transistor (DHBT) with 0.5μm emitter width. The technology offers four level of gold interconnect with BCB dielectric, and thin-film resistor and MIM capacitor are available. Return-to-Zero (RZ) current switches are added to current steering DAC for high frequency wideband applications to achieve higher than 1GHz bandwidth. When clocked at 2.3GHz, the DAC output measures better than 60dB spurious-free dynamic range (SFDR) at 1GHz output frequency. With 2.7GHz data clock and 8.1GHz RZ clock, the measured performance is >;50dBc SFDR at 8GHz output frequency. The chip measures 1450 × 2100μm including bonding pads and dissipates 1.6 watt power.

A single-chip direct digital frequency synthesizer with hardware efficient phase-to-amplitude mapping and an integrated DAC achieves over 50dB SFDR in full-Nyquist band at 1.7GHz clock frequency for synthesized output signals up to 850MHz. The IC is implemented in a 0.35 /spl mu/m SiGe BiCMOS process and occupies an area of 4.8/spl times/5.0mm/sup 2/. Power efficiency is 1.76mW/MHz at 3V.

RZ current switches are added to a current steering DAC for high-frequency wideband applications to achieve 800MHz bandwidth at 1/sup st/ and 2/sup nd/ Nyquist band without the need for a reverse sinc equalization filter. Implemented in a GaAs HBT process with 4.5 /spl mu/m/sup 2/ minimum emitter area, the DAC dissipates 1.2W at -5V with a 1.6GHz clock and 0dBm typical output power.

This paper presents a 1-GS/s, 12-bit SiGe BiCMOS D/A converter combined with high-speed low-spurious BiCMOS current switches and an efficient calibration method for current mismatch. Experimental results show a reduction in INL and DNL errors from +35.5/-62.2 LSB to +4.1/-3.4 LSB and from +8.1/-10.3 LSB to +6.2/-1.2 LSB, respectively, after calibration. SFDR performance is 72.3 dBc at output frequency of 1.82 MHz and 50.0 dBc at output frequency of 334.39 MHz, when the sampling clock frequency is 1 GHz. Power consumption is about 950 mW at 100.48MHz output frequency and -3.3 V power supply.

This paper presents a current calibration technique for systematic mismatch in current-cell array. The proposed technique is suitable for GHz-range current-steering D/A converters because of an efficient and totally independent calibration operation. Behavioral simulation and measurement results show that static and yield performance of a D/A converter can be enhanced significantly by using the proposed technique. A measured reduction in INL and DNL errors before and after calibration is from +33.2/-60.1 LSB to +1.28/-1.28 LSB and from +10.2/-12.8 LSB to +2.56/-1.28 LSB in 12-bit resolution.

When applied to folding ADCs, pipelining relieves the wide bandwidth requirement of the folding amplifier. A pipelined folding ADC prototyped using a 0.5 /spl mu/m CMOS process exhibits a DNL of /spl plusmn/0.4 LSB and an INL of /spl plusmn/1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm/spl times/1.2 mm in active area and consumes 165 mW at 5 V.