A power-rail electrostatic discharge (ESD) clamp circuit for monolithic GaN-based integrated circuits (ICs) with ultralow leakage current and dynamic timing-voltage detection function was proposed, which has been successfully verified in a 0.5-mu m GaN-on-Si process. The standby leakage current is only 0.8 nA. With the voltage detection, the proposed ESD clamp circuit can only be triggered by ESD events, and cannot be falsely triggered during fast power-on conditions. The experimental results demonstrate that the human-body-model (HBM) ESD robustness of the proposed design can be achieved over 6 kV. The triggered voltage of the ESD clamp circuit is flexible by adjusting the number of diode-connected high electron mobility transistors (HEMTs), so it can be utilized in different voltage ratings of V-cc.

Integrated circuits are susceptible to electrostatic discharge (ESD) events. Real-time detection and alerting of ESD events in semiconductor manufacturing environments is the key to achieving well ESD control. Additionally, the magnitude and duration of an ESD event are strongly correlated with the specific type of ESD events. The development of a novel ESD event detector, integrated on a single chip and featuring a logarithmic amplifier, a magnitude discriminator, and a time discriminator, has been motivated by this. This detector has been designed and fabricated in a 0.18- $\mu $ m CMOS process. The magnitude of the ESD event can be detected and converted to 5-bit digital output codes, whereas the time duration of the ESD event can be converted to 3-bit digital output codes by the newly developed ESD event detector. It has been proven in field applications that the detected ESD events can be successfully transmitted to the ESD control center through the RF Wi-Fi module, enabling real-time ESD monitoring and control in manufacturing environments.

For IC products, the I/O pins of CMOS integrated circuits (ICs) must be verified by latch-up I-test with the JEDEC JESD78F.01 standard. The high-voltage (HV) circuits and the low-voltage (LV) circuits have been integrated together in a single chip by the Bipolar-CMOS-DMOS (BCD) technology. The LV circuits were often surrounded by the n-type buried layer (NBL) isolation ring from the common p-type substrate. In the mixed-voltage IC, a parasitic latch-up path exists from the 5 V-tolerant I/O to NBL isolation ring in a 0.18- $\mu $ m BCD technology, which will cause the IC products failed to pass the latch-up I-test. In this work, a new isolation ring with embedded Schottky-barrier diode (SBD) was proposed and verified to overcome such a latch-up issue. According to the silicon results, the proposed Schottky-embedded isolation ring can significantly increase the holding voltage of the parasitic latch-up path. The potential latch-up danger from the 5 V-tolerant I/O to NBL isolation ring can be fully solved by the proposed Schottky-embedded isolation ring. In addition, the proposed Schottky-embedded isolation ring is fully process-compatible to the 0.18- $\mu $ m BCD technology without additional mask layer adding into the process flow.

When more circuit functions are integrated into a single chip fabricated by GaN-on-Silicon process, the on-chip electrostatic discharge (ESD) protection design shall be provided to protect the GaN integrated circuits. In this work, ESD robustness of E-HEMT GaN devices was investigated through test structures that fabricated in a GaN-on-Silicon process. The experimental results showed that the ESD robustness is proportional to the device dimension when the GaN device was operating in the forward mode. In addition, with the gate-coupled design, the ESD level of E-HEMT GaN device can be further improved. Based on the investigation results of this work, the whole-chip ESD protection scheme can be successfully realized by E-HEMT GaN devices.

This is the first study related to the latchup issue in the SiC process. In this work, the latchup risk and the holding voltage of the parasitic latchup path have been investigated. The dc holding voltage of the parasitic latchup is only 14.9 V, which is below the voltage rating (20 V) of the devices. The holding voltage measured by the transmission line pulse (TLP) system decreases when the pulsewidth increases, which can be attributed to the self-heating effect on the device. Moreover, the holding voltage measured by TLP decreases as the temperature increases. The methods to prevent latchup events are summarized in this brief. The methods can be divided into two parts. One is the process solution, and the other is the layout solution. Therefore, the design rules for latchup prevention in the SiC process must be developed.

Abstract The occurrence of electrical overstress (EOS) failure in low-voltage core circuits resulting from latch-up test at the I/O pins was investigated, where a specific commercial IC product equipped with on-chip low-dropout regulator (LDO). Through failure analysis experiments, the root cause of EOS failures is identified to the abnormal LDO output voltage during latch-up test. In this work, a modified design featuring a deep n-well (DNW) beneath the NMOS region is proposed to mitigate EOS issue by enhancing electron absorption. Additionally, compensation network configurations are explored to explain the abnormal LDO operation. The experimental results from test chip have validated the effectiveness of the proposed modifications, emphasizing the importance of proactive measures in mitigating EOS failures.

Deep brain stimulation is a standard neurosurgery to treat advanced Parkinson’s disease patients. An innovative technology known as closed-loop deep brain stimulation is under development. This technology aims to identify abnormal biomarker signals within the brain, and create novel systems featuring sophisticated hardware configurations to generate improved therapeutic approaches and more favorable outcomes. The primary challenge faced in advancing closed-loop deep brain stimulation is managing artifacts induced by electrical stimulation within the signal detection module. A notable circuit design challenge involves continuously monitoring local field potential alterations during electrical stimulation. The artifacts arising from the stimulation can be categorized into common-mode artifact voltage and differential-mode artifact voltage. Within this article, a comprehensive review encompasses recent methodologies designed to mitigate common-mode artifact voltage and differential-mode artifact voltage in local field potential through hardware-centric techniques, including filtering, template removal, blanking, and selective sampling. The inherent strengths and limitations of these strategies are compared and discussed. This article allows engineers to recognize appropriate artifact removal techniques to achieve a implantable closed-loop deep brain stimulation system. To this end, a more intelligent and more precise system could be developed for the treatment of Parkinson’s disease and other neurological disorders.

A new ESD-event level detector has been designed and fabricated in a 0.18-mu m CMOS process. The experimental results showed that it can detect ESD events generated from different kinds of ESD sources, including CDM ESD tester and IEC ESD generator. The core size of the silicon chip is only 550 x 305 mu m(2) realized in a 0.18-mu m CMOS process. In addition, it can be further used to form an ESD-event level detection system for monitoring the real-time ESD events in the manufacturing environments.

Charged-device model (CDM) electrostatic discharge (ESD) event is a complex reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, various circuit blocks have been integrated into a single chip. In order to avoid noise coupling between circuit blocks or even to reduce power consumption, the SoC chip was often equipped with separated power domains for different circuit blocks. However, the cross-domain interface circuits between different power domains are particularly susceptible to gate-oxide rupture caused by CDM ESD during cross-domain ESD events. In this study, CDM ESD robustness of cross-domain interface circuits with deep N-well (DNW) was investigated through test structures fabricated in a 0.18-μm CMOS technology.

In the harsh environment of field applications, the I/O pins of integrated circuit (IC) must be verified through latch-up test with current trigger, according to the standard of JEDEC JESD78F.01. This work presented a specific latch-up challenge encountered in an IC product, where a multi-functional I/O buffer is designed for LCD drivers. Such a multi-functional I/O buffer suffered a failure in latch-up (LU) I test, due to the indirect connection on the N-well of output PMOS to the power supply through a bias switch. To address this LU failure issue, this work thoroughly examines the failure mechanism and proposes an innovative solution. By using an embedded deep-nwell collector, the latch-up immunity of multi-functional I/O buffer with indirect power-connected N-well can be significantly improved.

For safe application of IC products, ensuring the integrity of CMOS integrated circuits (ICs) necessitates the verification of I/O pins through latch-up I-test that conforming to the standard of JEDEC JESD78F. The integration of high-voltage (HV) and low-voltage (LV) circuits within a single chip has been achieved in BCD technology. Typically, the LV circuits must be surrounded by an N-type buried layer (NBL) isolation ring to mitigate noise interference from the common p-substrate. However, in a mixed-voltage IC utilizing in 0.18-μm BCD technology, an unexpected parasitic latch-up path emerges from the 5V-tolerant I/O circuits to the NBL isolation ring. Such an unexpected parasitic latch-up path would fail the IC products to pass the requested latch-up I-test. Identifying such a latch-up risk has been practically verified in this study.

When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled design, fabricated in a GaN-on-Silicon process, was investigated. By increasing the gate-coupled capacitance, ESD level of the powerrail ESD clamp circuit can be significantly improved. However, the increased capacitance induces transient leakage current during normal power-on operation. To overcome this issue, a new detection circuit was proposed, which can differentiate between the ESD event and the normal power-on transient operation. Therefore, incorporating this new proposed detection circuit with the gate-coupled design allows for good ESD robustness, while also preventing transient leakage current during normal power-on condition.

The electrical safe operating area (eSOA) of the transmission-line pulse (TLP) test and the electrical behavior of the unclamped inductive switching (UIS) test on a 4H-SiC 600-V vertical double-implanted MOSFET (VDMOSFET) were investigated in this work. The snapback phenomenon of the 100-ns and 1000-ns TLP I-V curves can be inferred to be the triggering on of the parasitic BJT in the VDMOSFET. Moreover, the holding voltage of the 1000-ns TLP I-V curve was lower than that of the 100-ns TLP I-V curve, which can be attributed to the severer self-heating effect in the 1000-ns TLP test. In the UIS test, different experiments were conducted by varying pulse widths, gate resistances, and external inductors. The longer the falling time of the gate bias applied to the VDMOSFET, the lower the overshooting peak voltage on the drain side will be. Furthermore, the methods for improving the eSOA characteristic and the UIS ruggedness were also discussed and summarized in this work.

Deep Trench Isolation (DTI) is a specialized isolation technique employed in the BCD process to mitigate latch-up issues. Unlike junction isolation, which was typically implemented by guard rings, the DTI offers a significant reduction in layout area due to its physical isolation capabilities. This study delves into the impact of DTI on latch-up immunity between 100-V LDMOS in the I/O circuits and the additional guard ring between the 100-V I/O circuits and 5- V internal circuits. The results of this study will be benefit to the high-voltage IC products, that drawn with reduced layout spacing but having high latch-up immunity.

A dual-configuration dual-mode 8-channel high voltage stimulator is proposed and designed for biomedical applications. Dual-configuration indicates the choice between a bipolar or monopolar structural arrangement, while dual-mode refers to the selection between constant current or constant voltage stimulation. With supply voltages of 1.8 V, +/- 5 V, +/- 10 V, and +/- 15 V, the range of stimulus current is +/- 0.2 mA to +/- 10 mA with a 0.2 mA/step increment, and the range of stimulus voltage is +/- 0.2 V to +/- 10 V with a 0.2 V/step increment. The 8-channel stimulator chip has been fabricated in a 0.18-mu m BCD process with a silicon area of 3570 mu m x 1636 mu m. Moreover, stimulus functions have been successfully verified through experiments in agar with Pt electrodes and in-vivo animal test on pig with DBS electrode.

A CMOS analog front-end (AFE) local-field potential (LFP) chopper amplifier with stimulation artifact tolerance, improved right-leg driven (RLD) circuit, and improved auxiliary path is proposed. In the proposed CMOS AFE LFP chopper amplifier, common-mode artifact voltage (CMAV) and differential-mode artifact voltage (DMAV) removal using the analog template removal method are proposed to achieve good signal linearity during stimulation. An improved auxiliary path is employed to boost the input impedance and allow the negative stimulation artifact voltage passing through. The common-mode noise is suppressed by the improved RLD circuit. The chip is implemented in 0.18-μm CMOS technology and the total chip area is 5.46-mm2. With the improved auxiliary path, the measured input impedance is larger than 133 MΩ in the signal bandwidth and reaches 8.2 GΩ at DC. With the improved RLD circuit, the measured CMRR is 131 – 144 dB in the signal bandwidth. Under 60-μs pulse width and 130-Hz constant current stimulation (CCS) with ±1-V CMAV and ±50-mV DMAV, the measured THD at the SC Amp output of fabricated AFE LFP chopper amplifier is 1.28%. The measurement results of In vitro agar tests have shown that with ±1.6-mA CCS pulses injecting to agar, the measured THD is 1.69%. Experimental results of both electrical and agar tests have verified that the proposed AFE LFP chopper amplifier has good stimulation artifact tolerance. The proposed CMOS AFE LFP chopper amplifier with analog template removal method is suitable for real-time closed-loop deep drain stimulation (DBS) SoC applications

Deep Trench Isolation (DTI) is a specialized isolation technique employed in the BCD process to mitigate latch-up issues. Unlike junction isolation, which was typically implemented by guard rings, the DTI offers a significant reduction in layout area due to its physical isolation capabilities. This study delves into the impact of DTI on latch-up immunity between 100-V LDMOS in the I/O circuits and the additional guard ring between the 100-V I/O circuits and 5-V internal circuits. The results of this study will be benefit to the high-voltage IC products, that drawn with reduced layout spacing but having high latch-up immunity.

The development of the closed-loop deep brain stimulator (DBS) for clinical trials requires verification of its safety and effectiveness in a large animal model. Due to the financial and ethical challenges of using non-human primates, it is reasonable to use an alternative large animal model. It was reported that minipigs are suitable for the establishment of the MPTP-induced parkinsonian model. However, there is currently no evidence of whether beta oscillations, the symptom-related biomarker, exist in the subthalamic nucleus (STN) of the parkinsonian minipig model. This study was to verify whether the beta oscillations could be recorded in the STN of the parkinsonian minipig model. Parkinsonism was induced by injections of the 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP). Through a protocol involving up to nine subcutaneous or intramuscular injections, delivering a cumulative dose of 8-10 mg/kg MPTP, the minipigs developed notable movement disturbance. By stereotactic surgery and microelectrode recording, beta oscillations were recorded in the STN of the MPTPinjected minipigs. Immunohistochemistry of the tyrosine hydroxylase (TH) was performed in the substantia nigra pars compacta (SNc) of each animal. Compared with the control animal injected with saline, the THpositive cells in the SNc were significantly reduced in the MPTP-injected minipigs. This study showed that beta oscillations could be recorded in the STN of the MPTP-induced parkinsonian minipig model. This large animal model is suitable as an alternative pre-clinical model for developing closed-loop DBS in the future.

In high-power MOSFET, during the transient switching moment from on-state to off-state, it would suffer high V DS voltage and high I DS current in a short period at the same time. Hence, safe operating area (SOA) is always an essential characteristic that must be considered when power modules were designed. It this study, two methods (TLP and UIS) to characterize SOA of a 600V vertical double-implanted MOSFET (VDMOSFET) fabricated by SiC process were performed. From the results of TLP measurement, it was found that the triggered voltage $(V_{t1})$ decreased with the increment of gate bias $\boldsymbol{(V_{GS})}$ . The snapback phenomenon was also observed in the TLP-measured $\boldsymbol{I_{ds}-V_{ds}}$ curve. To acquire the stable holding characteristic after VDMOSFET breakdown during UIS testing, a current-limiting resistance was used to prevent the device from burning out directly. Nevertheless, even though the device size of VDMOSFET was large enough (around $\boldsymbol{180\mathrm{k}\mu\mathrm{m})}$ , it would still be burned out during the UIS testing with Vcc bias of only several hundred volts.