Temporal interference stimulation (TIS) has emerged as a promising neuromodulation technique for achieving deep brain stimulation (DBS) with reduced invasiveness. However, conventional transcutaneous TIS suffers from the current shunting effect from the scalp, which limits the electric-field (E-field) delivery to the target region. In addition, conventional sine-based TIS systems rely on noise-sensitive and linearity constrained analog waveform synthesizers. To address these limitations, this work presents a minimally invasive square-based TIS integrated circuit (IC) that simultaneously achieves enhanced E-field delivery and fully digital stimulation waveform generation. The system generates temporal interference (TI) envelopes by digitally controlling an ON/OFF H-bridge driver, significantly simplifying circuit implementation with a gate-driving overhead of only 250 nW per channel. It also delivers higher root-mean square (RMS) energy than sine-based TIS under identical peak-current conditions. The stimulation IC is integrated within a 0.96 mm2 active area. Experimental tissue phantom measurements show that the proposed system achieves a 2.01 dB higher PSD at Δf and a time-domain envelope amplitude approximately 1.27 times that of sine-based TIS, demonstrating enhanced Δf envelope delivery. The proposed system supports long-term operation (1 s-1 h) and real-time parameter control through an inductive-link interface. It also achieves one of the lowest reported system complexities. These results demonstrate the feasibility of a programmable wireless TIS system for the proposed minimally invasive on-skull configuration.
Conventional wireless approaches for wearable body sensor networks suffer from body shadowing effects and high power consumption. Human body communication (HBC) utilizing the body's conductive properties offers a promising alternative but faces challenges from dynamic channel characteristics and environmental interference coupling in the sub-10 MHz electro-quasi-static (EQS) regime. To mitigate interference effects, existing transceivers employ narrowband operation with conservative carrier-to-data-rate ratios. This paper presents an interference-aware adaptive frequency hopping (AFH) HBC transceiver operating below 10 MHz, where AFH is realized as interference-driven adaptive channel selection. The proposed AFH on-off keying (OOK) transceiver integrates a tiny on-chip microcontroller unit (MCU) enabling autonomous frequency hopping control, real-time channel assessment, and direct sensor interfacing. Fabricated in 65-nm CMOS occupying 0.117 mm2, the transceiver achieves 22-360 kbps data rates, -33 dB signal-to-interference ratio (SIR) tolerance at bit error rate (BER) of 10-3, and 40× BER improvement over single-frequency operation at maximum body distance of 180 cm. The transceiver achieves 62.2-79.5 pJ/bit energy efficiency, enabling extended battery life for distributed wearable applications, while benefiting from the inherent security of the sub-10 MHz EQS regime.
High-performance neuromodulators make essential contributions to the treatment of major neurological disorders and quality of life improvement. To enhance therapeutic efficacy and address safety challenges associated with long-term implanted neuromodulators, several high-performance techniques are proposed in this work. Firstly, a novel redundant current mapping (RCM) technology is developed to improve stimulation resolution at minimal area cost. Secondly, a new power-efficient self-adaptive pulse-width calibration (SAPCA) charge-balancing (CB) scheme ensures long-term stimulation safety. Thirdly, several compliance-extension techniques have been developed to achieve a voltage compliance of±11 V. The ASIC is fabricated in a 180-nm Bipolar-CMOS-DMOS (BCD) process with an area of 0.285 mm2/ch. Measurement results show that it achieves 14.5-bit resolution over a 6.5-mA current range and 12.8-bit resolution over a 10-mA current range. The residual voltage (Vres) is reduced from several V to ±5 mV consuming 1.74 μW. Besides, an in vivo experiment demonstrates that the ASIC can maintain CB under long-term stimulation, thereby preserving chronic neuromodulation safety.
Real-time electroencephalogram (EEG) processing on wearable platforms faces strict latency, power, and resource constraints, making efficient finite impulse response (FIR) filtering a critical challenge. Many representative field-programmable gate array (FPGA) solutions rely on manual design or vendor-supplied intellectual property (IP) cores, which can limit portability and signal-aware optimization across different signal specifications. This work presents AutoFIR, an automated co-design framework that translates high-level EEG filtering specifications into FPGA-based FIR implementations. AutoFIR integrates signal-aware quantization, shift-add approximation, and systematic architectural optimization to balance signal fidelity, arithmetic complexity, and hardware parallelization. Offline feedback from C-simulations and post-HLS synthesis estimates is used to screen and compare candidate designs within a staged design exploration flow under memory-access and scheduling constraints. On the evaluated Zynq-7020 platform, AutoFIR generates a DSP-slice-free implementation that achieves a 5.22× latency reduction over the unoptimized baseline while maintaining filtering fidelity under the current EEG dataset and filter specification. These results suggest that coordinated, signal-aware automation is promising for the evaluated resource-constrained EEG FIR filtering scenario.
In wireless photoplethysmography (PPG) systems, motion artifacts (MAs) and high-power consumption of PPG data acquisition are the critical bottlenecks. MAs induced by body movement during long-term wear significantly degrade PPG signal fidelity, thereby increasing post-processing power consumption. Although previous studies have investigated MA mitigation, power optimization, and wireless connectivity independently, their co-design and system-level integration remains largely unexplored. This paper presents a motion-controlled wearable (MCW) wireless PPG sensing system that features an autonomous motion-gated sampling technique, adaptive power management, and robust data transfer via a metamaterial-enhanced telemetry link. The MCW system autonomously employs motion-gated sampling to acquire heart rate (HR) and blood oxygen saturation (SpO2) data under different physical activities. The motion-gated sampling algorithm reduces system power consumption by 55% from its active mode while ensuring robust physiological measurements accuracy. Experimental results demonstrate Mean Absolute Errors (MAEs) ranging from 1.5-6.2 BPM (HR) and 0.5-1.0 % (SpO2) across sitting, standing, walking, and running motions, while maintaining PPG signal-to-noise ratio 10 dB under all evaluated activities. Additionally, integrating an electromagnetic bandgap (EBG) structured metamaterial enhances the on-body antenna's performance and decreases the specific absorption rate (SAR) from 4.36 W/kg to 1.677 W/kg. The proposed MCW system, encapsulated in silicone, provides a compact, energy-efficient platform for reliable long-term wearable cardiovascular monitoring.
Wireless ingestible sensing capsules are of high relevance in the medical field due to their capability to measure biochemical parameters along the gastrointestinal (GI) tract and the potential to associate these with health-related conditions. Obtained sensor information is much more valuable when accompanied by accurate localization, since propagation speed can vary widely. However, most capsule localization systems presented in literature are either not accurate enough or imply bulky external units difficult to wear during daily life activities. Here, a novel ingestible sensing capsule ‘GISMO-LOC’ for pH and oxidation reduction potential sensing is presented. It features magnetic localization functionality enabled by a wearable transmitter belt. An in-vitro evaluation of the biochemical sensors confirmed the expected biochemical sensing functionality of the capsule. Evaluations of the location estimation in controlled conditions resulted in a mean absolute error (MAE) of 5.7 mm in the volume of interest. A GI trajectory reconstruction using a robot is also presented, with a MAE of 3.8 mm. An on-human evaluation during typical daily life activities resulted in most absolute errors below 2 cm for ‘light’ activities, 3 cm for ‘moderate’ activities and 4 cm for high-motion activities such as running. An evaluation of the belt comfort showed volunteer willingness to wear the belt during one week in daytime, while improvement aspects were identified to enable its use during the night. Finally, a limited in-vivo validation of the localization in an animal model was successfully performed. GISMO-LOC is therefore presented as a novel tool for GI tract related research.
High-density neural interfaces require power-efficient acquisition and on-chip processing for low-latency closed-loop operation. While level-crossing ADCs (LC-ADCs) offer efficient front-end acquisition, their integration with large-scale on-chip spike-sorting remains unexplored. In addition, existing on-chip spike sorters rely on temporal or spatial features alone, or on high-dimensional snippets, limiting the accuracy and efficiency. To address these limitations, this work presents a 128-channel neural digitization and spike-sorting system-on-chip (SoC) in 22-nm FDSOI CMOS, introducing three main novelties. First, a synchronized LC-ADC front-end coupled with pulse-domain spike detection reduces the detection power and area by 15.34% and 37.96% compared to NEO-based approaches with negligible accuracy loss. Second, a spatial spike realignment module corrects noise-induced electrode misalignment, improving the accuracy by 6.83%. Third, a compact spatiotemporal feature extractor uses 8 features to improve the accuracy by up to 9.18% while reducing the hardware cost. The chip consumes 1.2 µW and 0.00176 mm2 per channel for recording, and 1.09 µW and 0.0016 mm2 per channel for on-chip spike sorting. These results demonstrate the first large-scale co-integration of a synchronized LC-ADC front-end with hardware-efficient spatiotemporal spike sorting, enabling scalable and low-power neural interfaces.
This work presents a PET-oriented double-ring Vernier time-to-digital converter (DRVTDC) that targets the timing-quantization block required in multi-voltage-threshold (MVT) and time-over-threshold (ToT) front-end readout for time-of-flight (ToF) positron emission tomography (PET) applications. This work addresses two critical error mechanisms that limit the use of multi-stage Vernier TDCs: parallel output misalignment (POM) between quantization stages and mismatch-induced chasing error (MCE) in the Vernier arbiter array. To suppress these errors, a joint calibration scheme combining code error cancellation (CEC) and Vernier arbiter phase calibration (VAPC) is proposed. The core TDC achieves a 10.4-ps resolution with only 0.0075 mm2 core area. The implemented 7-bit coarse counter provides a dynamic range (DR) of 5.12 μs. Empowered by these techniques, the measured DNL and INL ranges are significantly improved from +3.17/-0.89 LSB and +7.0/-6.9 LSB to +0.34/-0.29 LSB and +1.15/-1.09 LSB, respectively, alongside a 26-dB enhancement in the SFDR. The core TDC consumes 1.758 mW, with a total of 5.526 mW including the PLLs.
We aimed to develop a scalable, low-power graphene field-effect transistor (GFET) crossbar array integrated with a neural-interface system-on-chip (NISoC), termed the GFET-NISoC platform, for multiplexed, real-time biomolecular sensing, including ultra-sensitive detection of Pb2+ using a G-quadruplex ssDNA aptamer. A 12×12 GFET crossbar array was fabricated using a multilayer dielectric stack and optimized graphene transfer. Characterization was performed using both benchtop instrumentation and a low-power NISoC front-end supporting current- and voltage-clamp modes. Ionic strength, pH, and Pb2+ dose-response measurements were obtained from functionalized arrays. The platform demonstrated uniform Dirac behavior, reversible pH-dependent conductance, predictable ionic-strength responses, and femtomolar-level Pb2+ detection with strong selectivity over Ca2+ and Co2+. The GFET-NISoC system enables multiplexed, multi-modal sensing at sub-μW power levels and provides a promising foundation for wearable or point-of-care chemical and biomolecular monitoring.
This paper presents a chopper-stabilized capacitively coupled instrumentation amplifier (CS-CCIA) that achieves large electrode DC offset (EDO) cancellation while featuring a short recovery time and GΩ-level input impedance (Zin). Through analyzing the constraints of noise contribution and recovery time on traditional DC-serv oloops (DSL), a feedforward assisted DSL (FFA-DSL) scheme is proposed. By combining a feedforward SAR ADC for coarse EDO cancellation and an analog DSL (ADSL) for residual offset suppression, the FFA-DSL scheme achieves fast recovery from large EDO steps with low noise contribution. A hybrid positive feedback loop (PFL) is proposed to boost the AC Zin and the DC resistance of the CCIA simultaneously. Additionally, a common-mode cancellation loop based on voltage feedback (FB-CMC) is designed to suppress common-mode interference (CMI) without introducing additional capacitive loading at the input. Fabricated in a 0.18µμm CMOS process, the CCIA achieves ±1 Vpp EDO cancellation with a 2.1-s ADSL recovery time after the feedforward path is activated (trec), while delivering a worst-case total recovery time (ttot) of 4.37 s at a 0.5 Hz high-pass corner frequency. It also provides 1-Vpp CMI tolerance, 2 GΩ Zin at 0.1Hz, and 1.8-μVrms input-referred noise within frequency range of 1 Hz to 200 Hz. It consumes 2.16 μW from a 1.2-V supply.
Spiking Neural Networks (SNNs) have emerged as a promising paradigm for brain-inspired edge computing. Leveraging binary spikes and local learning rules, SNNs enable energy-efficient on-chip learning and rapid adaptation to changing environments, which is crucial for edge AI that needs to learn continuously from new data. However, many SNN processors enabling on-chip learning for edge computing confront a trade-off: small-scale task-specific designs offer low power but poor multi-task inference accuracy, while large-scale general-purpose designs achieve high multi-task accuracy at the cost of large memory and poor energy efficiency. To overcome this challenge, this paper presents ANP-R, a 22nm asynchronous SNN-based edge AI processor with coarse-grained reconfigurable architecture enabling one-shot, few-shot, batch and incremental on-chip learning. The processor integrates 64 cores containing 4096 neurons and 0.262 million synapses. Two key features are proposed: 1) An asynchronous coarse-grained reconfigurable architecture that supports various STDP-based SNN topologies. These topologies enable over 95% average accuracy across four sensory tasks; 2) an energy-efficient asynchronous training method incorporating a self-adaptive synaptic weight update mechanism reducing up to 65% redundant updates without accuracy loss, and a trained weights low-bit width coding method reducing up to 50% storage cost with 0.3% accuracy loss. Measurement results demonstrate 92.1% accuracy for hand gesture classification, 93.9% for keyword spotting, 98.6% for object recognition and 99.2% for gas identification. Compared with state-of-the-art SNN-based chips, this work achieves up to 6.02x, 8.61x and 7.1% improvement in energy efficiency, energy per step, and accuracy, respectively.
This paper presents an energy-efficient photoplethysmography (PPG) sensor IC with adaptive windowing for low-power wearable monitoring. By utilizing the first derivative of the PPG signal (i.e., the velocity of PPG, VPG), the proposed algorithm tracks the PPG peaks and valleys (PAVs), enabling higher sampling rates only when necessary. Validated on the BIDMC dataset, the proposed VPG-based method reduces the PAV missing rate from 9.90% to 3.81% compared with the period-based algorithm. Additional BIDMC evaluations under additive noise and periodic artifact injection characterize its operating boundary, while representative walking examples from the PTT dataset illustrate PAV tracking under real motion-degraded conditions. The proposed IC, fabricated in a 180-nm CMOS process, is validated through in vivo measurements against a clinical-grade reference device. The system achieves mean absolute errors (MAEs) of 0.73 bpm for heart rate and 0.53% for SpO2, while reducing the total power consumption to 10.42 μW per channel, corresponding to a 53% reduction. These results demonstrate a practical low-power PPG sensing solution for wearable monitoring.
Adaptive closed-loop neuromodulation is an emerging therapeutic paradigm for treating neurological and psychiatric diseases. However, its hardware implementation remains challenged by limited regulation accuracy, high latency & energy overhead, and poor cross-workload compatibility. To address these faced challenges, this article presents a multi-task neural processing system-on-chip (SoC) with three key technologies. First, an established multi-input multi-output linear state-space model (MIMO LSSM) with linear quadratic Gaussian (LQG) control is configured for deterministic on-chip execution to improve regulation accuracy. Second, a processing element (PE)-array-aware compact parameter-encoding scheme is proposed to reduce storage cost and memory-access overhead. Third, a mode-configurable compute fabric (MCCF) is designed to support diverse neuromodulation workloads on a unified hardware fabric. The designed SoC was fabricated in a TSMC 65nm CMOS process. Measured results and performance comparison show that it achieves a maximum energy efficiency of 1.43 TOPS/W (3.08×), a maximum area efficiency of 1.09 GOPS/mm2 (13.29×), and a peak performance of 5.12 GOPS (40.96×). Besides, the SoC has been demonstrated on the BONN and DEAP datasets, achieving accuracies of 99.18% in seizure detection and 92.3% in emotion detection. Overall, the proposed SoC offers a competitive hardware solution for adaptive closed-loop neuromodulation.
This paper presents a proof-of-concept ultra-low voltage and ultra-low-power chronoamperometric sensing platform for non-enzymatic glucose detection, based on the co-design of a reconfigurable digital-based (DB) potentiostat and a mesoporous platinum (Pt) microelectrode. The DB potentiostat enables current readout and direct digitization from a 0.3V supply at nanowatt-level power, while the microelectrode geometry and mesoporous Pt nanostructuring provide non-enzymatic glucose sensitivity at physiologically relevant concentrations within an electrochemical operating window compatible with the voltage and power constraints of the readout. A frequency-domain signal and noise model of the DB potentiostat is derived for the first time and validated through simulations and measurements, providing a quantitative basis for the electrochemical/readout co-design. Fabricated in 130nm CMOS, the DB potentiostat achieves 5.6 pArms input-referred noise, corresponding to a 16.8 pA circuit level minimum detectable current, while consuming 1.65nW at VDD=0.3V. Electrochemical currents from 600 pA to 650 nA are experimentally measured with R2=0.991 linearity under ferrocyanide test conditions. Non-enzymatic glucose measurements with mesoporous Pt microelectrodes at physiologically relevant concentrations, under aerobic conditions and with ascorbic acid as an interferent, demonstrate, to the best of the authors’ knowledge, the lowest reported power consumption for CMOS non-enzymatic glucose readout, supporting the potential of the proposed platform for emerging point-of-care diagnostics applications.
This paper presents a highly energy-efficient, low-jitter digital injection-locked phase-locked loop (ILPLL) tailored for the 2.4 GHz industrial scientific medical band. The proposed digital injection-locking architecture overcomes the limitations of conventional analog approaches regarding power, area, and robustness, and its incorporated differential multi-phase injection technique simultaneously suppresses jitter and further reduces power consumption. The misaligned injection pulse timing and non-optimized injection pulsewidth are digitally calibrated in background to maintain low power and low jitter across process, voltage, and temperature (PVT) variations. Fabricated in a 28-nm CMOS process, the proposed digital ILPLL achieves 542 fs RMS jitter with -65.8 dBc spur at 2.4 GHz working frequency. It consumes 820 ¼W power from a 0.6 V supply voltage, demonstrating the state-of-the-art energy efficiency along with a competitive jitter. In vitro experiment is conducted in a hospital for clinical trials, where the proposed digital ILPLL integrated into an SoC provides a local oscillator signal for the radio frequency front-end, enabling the system to wirelessly transmit electrocardiogram data in a battery-free manner.
This article presents the design and implementation of a highly integrated, low-power on-off keying (OOK) transceiver for energy-efficient wireless communication in the 2.4 GHz Industrial Scientific Medical band. The receiver integrates a novel single-to-differential envelope detector paired with an auto-feedback calibrator (AFC), thereby enhancing sensitivity while minimizing power consumption and chip area. By eliminating the need for a large-area balun and leveraging the AFC, the receiver optimizes signal detection performance. The transmitter incorporates a current-reused self-mixing voltage-controlled oscillator to reduce energy consumption, along with a quadruple-transconductance power amplifier to suppress second-order harmonic distortion. The entire transceiver is fabricated using TSMC 0.18 µm CMOS technology. For short-range operation at a carrier frequency of 2.45 GHz, the receiver achieves a sensitivity of -38.8 dBm at a 2 Mbps data rate. Meanwhile, the transmitter supplies 16.3 dBm output power and supports data rates of up to 30 Mbps. Operating from a 1.2 V supply, the receiver and transmitter consume only 8.7 µW and 0.856 mW, respectively. Overall, these results yield an energy-per-bit of 4.35 pJ/bit for the receiver and a figure of merit of 10.47 for the transmitter, highlighting the transceiver×s suitability for low-power, high-efficiency implantable or wearable applications.
AI-powered medical imaging devices are increasingly used in clinical workflows to support real-time, accurate diagnosis and decision-making. Recent advances in State-Space Models (SSMs) such as Mamba have shown remarkable performance in capturing long-range dependencies for medical image classification. However, their computational complexity and sequential data flow make them difficult to deploy on hardware, limiting real-time and energy-efficient applications at the edge. To address this challenge, we propose MedMambaLite-v2, a shared selective scan framework enabling effective acceleration on embedded edge platforms. For this aim, we build upon our earlier MedMambaLite, and further extend it in MedMambaLite-v2 through a channel-only transition mechanism that achieves a 1.7$\boldsymbol{\times}$ reduction in operations. We then optimize the Convolution (Conv) branch, and apply knowledge distillation to retain accuracy in a compressed student model. The resulting model is 23$\boldsymbol{\times}$ smaller compared to the MedMamba baseline, with only 1.1% reduction in the overall accuracy evaluated across 10 distinct MedMNIST datasets spanning several imaging modalities. The proposed LiteSS2D hardware design also leverages parallelism across scan directions to enable simultaneous state updates, thereby improving memory efficiency, and further incorporates 8-bit quantization to reduce computational overhead. The reconfigurable FPGA hardware prototype demonstrates 9$\boldsymbol{\times}$ reduction in latency for a parallel implementation compared with a serial baseline. Moreover, MedMambaLite-v2 is implemented and demonstrated through end-to-end inference on MedMNIST images on CPU and GPU platforms. Performance analysis of the proposed approach on NVIDIA Jetson Orin Nano and Raspberry Pi 5 shows up to 63% and 78% reductions in energy per inference, respectively, compared to the baseline.
This paper presents a single-stage single-coil wireless multi-channel adiabatic supply stimulation (M-CASS) system that generates four separate adiabatic supplies to independently regulate four constant stimulus currents, without using power-hungry current sources, regardless of stimulus current and load impedance. A wireless power distributor, combined with an AC-DC quadruple-output current regulator, independently controls four stimulus channels while receiving AC power from a single wireless link. A channel-optimized size control technique and a wide adaptive offset control scheme are employed to enhance the peak AC-to-stimulation efficiency in wireless adiabatic stimulation. The 2.72 mm2 0.25-μm CMOS M-CASS demonstrates four independently controlled stimulus currents with four adiabatic supplies over a 6.78-MHz resonant link. Furthermore, M-CASS achieves a peak AC-to-stimulation efficiency of 82.2% when steering four 2-mA currents and maintains approximately 80% efficiency even when the four channels experience different impedances and currents. These features of M-CASS using a single coil provide a compact and energy-efficient solution for multiple-source current-steering (MSCS) deep brain stimulation (DBS) applications.
