In the world of Integrated Circuits, Complementary Metal–Oxide–Semiconductor (CMOS) has lost its credentiality during scaling beyond 32nm. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As a result of such SCE many alternate devices have been studied. Some of the major contestants include Multi Gate Field Effect Transistor (MuGFET) like FinFET, Nano tubes, Nano wires etc. In this work, the basic gates and memory circuits like DRAM are modeled in HSPICE software using CMOS structure and FinFET structures are analyzed and their performances like standby power Consumption and static noise margin are compared. Also a low power and robust DRAM cells based on FinFET has been proposed for 32nm technology.

Controlling the morphology of inorganic nanocrystals is important because many of their electronic attributes are highly sensitive to shape and aspect ratio. FePt nanocrystals have potential as advanced magnetic materials for ultrahigh-density memory. This is due to their high shape and/or magnetocrystalline anisotropy, which allows bits as small as 3 nm to be thermally stable over typical data storage periods of 10 years. Herein, nanocrystals were simply fabricated by simultaneous reduction of platinum acetylacetonate and thermal decomposition of iron pentacarbonyl in properly chosen conditions of solvent/surfactant proportions and temperature for rational design of their shape and magnetic properties. This work has combined magnetometry measurements and micromagnetic simulations to illustrate the role of the external shape on the rotation of the magnetization vector for colloidal assemblies.

High-k gate dielectrics and metal gate electrodes are required for enabling continued equivalent gate oxide thickness scaling, and hence high performance, and for controlling gate oxide leakage for both future silicon and emerging nonsilicon nanoelectronic transistors. In addition, high-K gate dielectrics and metal gates are required for the successful demonstration of high performance logic transistors on high-mobility non-silicon substrates with high iON/iOFF ratios.

A method, comprising: Forming a gate dielectric layer of high-k on a substrate having a root mean square surface deviation in a measurement using the atomic force microscopy of less than about 0.3 nm (three angstroms).

We demonstrate for the first time 85nm gate length enhancement and depletion mode InSb quantum well transistors with unity gain cutoff frequency, fT, of 305 GHz and 256 GHz, respectively, at 0.5V VDS, suitable for high speed, very low power logic applications. The InSb transistors demonstrate 50% higher unity gain cutoff frequency, fT, than silicon NMOS transistors while consuming 10 times less active power

Several key emerging nanoelectronic devices, such as Si nanowire field-effect transistors (FETs), carbon nanotube FETs, and III-V compound semiconductor quantum-well FETs, are assessed for their potential in future high-performance, low-power computation applications. Furthermore, these devices are benchmarked against state-of-the-art Si CMOS technologies. The two fundamental transistor benchmarking metrics utilized in this study are: (i) CVII versus L/sub G/; and ii) CVII versus I/sub ON//I/sub OFF/. While intrinsic device speed is emphasized in the first metric, the tradeoff between device speed and off-state leakage is assessed in the latter. For high-performance and low-power logic applications, low CVII and high I/sub ON//I/sub OFF/ values are both required. Based on the results obtained, the opportunities and challenges for these emerging novel devices in future logic applications are highlighted and discussed.

Transistor, which comprises a gate electrode formed on a gate dielectric layer formed on a substrate; a pair of source / drain regions which are formed in the substrate on opposite sides of the mutually laterally opposite side walls of the gate electrode; and wherein the gate electrode has a central, formed on the gate dielectric layer over the substrate region between the source / drain regions portion and a pair of sidewall portions which overlap a portion of the source / drain regions wherein the central portion has a first work function and said pair of side wall portions have a second work function wherein the second work function of the first work function is different.

A method, comprising: Forming a sacrificial gate structure; Removing the sacrificial gate structure; Replacing the sacrificial gate structure by a metal gate electrode; Covering the metal gate electrode with a nitride layer; and Covering said nitride layer with an interlayer of kohlenstoffdotiertem oxide.

Sustaining Moore's Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore's Law will continue at least through early next decade. By combining silicon innovations with other nanotechnologies on the same Si platform, it is expected that Moore's Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotubefield-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications.

We show experimental evidence of surface phonon scattering in the high-/spl kappa/ dielectric being the primary cause of channel electron mobility degradation. Next, we show that midgap TiN metal-gate electrode is effective in screening phonon scattering in the high-/spl kappa/ dielectric from coupling to the channel under inversion conditions, resulting in improved channel electron mobility. We then show that other metal-gate electrodes, such as the ones with n+ and p+ work functions, are also effective in improving channel mobilities to close to those of the conventional SiO/sub 2//poly-Si stack. Finally, we demonstrate this mobility degradation recovery translates directly into high drive performance on high-/spl kappa//metal-gate CMOS transistors with desirable threshold voltages.

Sustaining Moore's Law of scaling Si CMOS transistors requires not only shrinking the transistor dimensions, but also the introduction of new materials and structures. In the future, advanced high performance CMOS transistors are likely to incorporate highly strained Si and SiGe channels for enhanced carrier transport and high-k/metal-gate stacks for low gate leakage. This work describes the recent advances made in integrating strained Si and SiGe channel transistors with high-k/metal-gate stacks for future high performance, low power logic applications.

We have successfully demonstrated very high-performance PMOS and NMOS transistors with high-K/metal-gate gate stacks with the right threshold voltages for both p- and n-channels on bulk Si. We believe that high-K/metal-gate is an option for the 45 nm high-performance logic technology node.

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5-2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

We integrate a strained Si channel with HfO/sub 2/ dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO/sub 2/, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO/sub 2//strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with 15nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.

In this paper, the performance and energy delay trends for research devices down to 10 nm and also discusses the 10 nm barrier and potential ways to break it were explored.

This paper reports, for the first time, the high-frequency response of NMOS and PMOS transistors in an integrated CMOS technology with 100 nm physical gate length and alternative gate dielectrics such as ZrO/sub 2/ and HfO/sub 2/ with TiN/PolySi gate electrode. It is shown that the dielectric constants of ZrO/sub 2/, HfO/sub 2/ and SiO/sub 2/ are invariant with respect to operating frequency at least up to 20 GHz. In addition, the cutoff frequency f/sub t/ of the 100 nm CMOS transistor test structures with ZrO/sub 2/ gate dielectric was measured to be equal to 46 GHz for NMOS and 47 GHz for PMOS. The corresponding f/sub t/ values for HfO/sub 2/ were 45 GHz for NMOS and 35 GHz for PMOS. High-K film transistors with 80 nm physical gate lengths, 7 /spl mu/m gate width and layout optimized for high frequency testing were also fabricated. The NMOS devices achieved an f/sub t/ of 83 GHz and an f/sub max/ of 35 GHz, while the PMOS yielded 41 GHz and 25 GHz respectively. These results are very similar to those of CMOS transistors with SiO/sub 2/ gate dielectric at similar physical gate lengths and widths. These results are very encouraging and suggest that high-K gate dielectrics can be used for high-frequency logic applications.

Soft X-ray spectroscopy was used to study the transport of the dominating impurity, carbon, in the central region of the Phaedrus-T tokamak in ohmic and high confinement mode (H mode) plasmas. These H modes were induced by an electrode positioned in the edge of the plasma and biased positive with respect to the limiter. The primary source of carbon in the Phaedrus-T tokamak plasma is the graphite limiter. A soft X-ray polychromator utilizing multilayer mirrors (MLM) as dispersive elements simultaneously monitored the Lyman alpha emission of H-I-like carbon at 33.7 AA, and the blended singlet and triplet transitions of He-I-like carbon at 40.3 and 40.7 AA, respectively, and spatially resolved their distributions in the plasma with a temporal resolution of 1 ms. The measured impurity emission profiles from the ohmic and H mode portions of hydrogen and deuterium plasmas were analysed with the Multiple Ionization State Transport (MIST) code in order to estimate the impurity transport in the plasma. Large increases in the impurity particle confinement time were observed as the plasma made the transition from ohmic to H mode, and the improvement in the impurity confinement was found to be greater in the deuterium plasmas. Comparisons were made between the emission profiles, which are used to probe the effects of the H mode deep inside the plasma, and the I-V characteristics of the biased electrode, which are used to monitor the edge of the plasma. The I-V characteristics of the biased electrode were found to have a direct impact on the carbon emission profiles

Following experimental demonstration of Alfvén Wave Current Drive (AWCD) on the Phaedrus‐T tokamak a redesigned high power antenna has been installed that couples 0.5 MW to the plasma. Evidence is shown for core electron heating coexisting with AWCD. There was no observable increase in the AWCD efficiency during these heating experiments, although the spread in kz launch made it difficult to determine if the ratio of wave phase speed to electron thermal speed was actually reduced and whether any decrease in efficiency due to changes in the electron trapping fraction occurred. Scans of toroidal magnetic field show systematic changes in the time dependence of the drop in loop voltage during the RF pulse. Reflectometer data indicates two radial locations for RF fluctuations.