In the world of Integrated Circuits, Complementary Metal–Oxide–Semiconductor (CMOS) has lost its credentiality during scaling beyond 32nm. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As a result of such SCE many alternate devices have been studied. Some of the major contestants include Multi Gate Field Effect Transistor (MuGFET) like FinFET, Nano tubes, Nano wires etc. In this work, the basic gates and memory circuits like DRAM are modeled in HSPICE software using CMOS structure and FinFET structures are analyzed and their performances like standby power Consumption and static noise margin are compared. Also a low power and robust DRAM cells based on FinFET has been proposed for 32nm technology.

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5-2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

The origins of the different power laws arising from hot carrier stressing at low and high gate voltages are examined. It is found that damage at V/sub g/=V/sub d/ (predominantly electron trapping in the oxide) has the same underlying 0.5 power law exponent dependence as stress under I/sub b(max)/ (interface state creation) conditions, if degradation is measured as a function of injected electronic charge instead of time. It is proposed that the reduced gradient normally seen under V/sub g/=V/sub d/ stresses arises due to the repulsive electrostatic oxide fields created by the trapped oxide charge and does not reflect the fundamental rate of trap creation. Stressing at low gate voltages (V/sub g/=V/sub d//5) also reveals the presence of a similar time power law of exponent 0.5 when the oxide trap contribution alone is separated out from the rest of the damage. It is concluded that the 0.5 power law appears to be the fundamental underlying kinetic equation that is seen throughout the gate voltage stress range, despite the different types of damage and the very different trap creation mechanisms.

The effect of nitriding and reoxidizing conditions are examined on the hot-carrier (HC) properties of p-channel and n-channel transistors with reoxidized nitrided oxide gate dielectrics. Nitrogen was introduced into the gate dielectric by performing cyclical nitridation and reoxidation steps (one cycle versus four cycles of nit./reox.), keeping the same overall oxidation and nitridation times constant, It was found that there were considerable differences in hot-carrier hardness, of up to three orders of magnitude for p-channel transistors, but much less for n-channel devices. Nitrogen-content variations (a factor of 2) for these very similar conditions explain the n-channel hot-carrier results. In the case of the p-MOS transistors, it is suggested that changes in hydrogen concentration might be responsible for the hot-carrier behavior.

SOI MOSFETs fabricated using LOCOS isolation can suffer from source-to-drain leakage along the edge of the silicon island which degrades the subthreshold slope of the device and increases the off-state leakage current. The edge leakage is caused by a parasitic edge transistor in parallel with the main transistor. This leakage is typically more common in NMOS devices because the boron at the tip of the silicon island readily segregates into the surrounding oxide. A technique has been demonstrated which can increase the V/sub T/ of the parasitic edge transistor in LOCOS-isolated NMOS devices, thereby dramatically reducing the parasitic edge leakage without greatly affecting the main transistor. In a research/development environment, this technique offers the possibility of extracting circuit data from a lot whose leakage otherwise prevents meaningful circuit measurement, and thus provides a tool for overcoming parasitic edge leakage without the need to run additional silicon.

Although hot carrier failure in very short channel (<0.35 μm) p-MOS transistors is often described in terms of threshold voltage (Vt) shifts, a more meaningful hot carrier indicator for dynamic logic is the leakage current, Id.off (measured at Vd = −3.6V, Vg = −0.1V). A new method for determining the hot carrier failure time based on the leakage current is proposed here. This method has the advantage of being independent of the initial threshold voltage. A relationship is proposed that links the leakage current to the effective length of the transistor. With this relationship, it is possible to quickly screen for whether devices meet the hot carrier criterion, by simply measuring the leakage current and the effective channel length.

Plasma-induced charging damage was examined on both bulk and SOI n-MOSFETs using time-zero dielectric breakdown measurements. It was found that the TZDB distributions for the SOI devices were less dependent on antenna ratio and less susceptible to antenna charging damage than bulk silicon devices. The dramatically different behavior for SOI implies that the antenna design rule requirements for bulk and SOI MOSFETs will not be the same. Finally, it is noted that antenna damage effects in SOI devices may depend on the size of the silicon island relative to the length scale of the plasma non-uniformity

A nitridation technique is proposed for ultrathin, SiO2 oxides in deep submicron CMOS technology, which involves direct implantation of molecular nitrogen (N-2) into the silicon substrate. N-2 ions were implanted into silicon at different doses and energies, through a 150 Angstrom thick screen oxide. In this study the effect of implanted N atoms on silicon oxidation, and SiO2 oxide nitridation process have been studied. Two groups of the N-2-implanted wafers were used: wafers from one group were annealed prior to the screen oxide removal, whereas wafers of the other group did not receive this anneal. It is shown that nitridation can be achieved both ways, allowing this technique to be easily integrated into a semiconductor IC fabrication process.

The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in Delta V-t for thinner oxides are found to play secondary roles.

We have investigated the impact of plasma-induced charging damage on the hot carrier reliability of n- and p-MOSFET's, including the examination of different stress bias regimes and the statistical distributions of hot carrier failure times. We found that when electron trapping determines hot carrier failure-as in p-MOSFETs stressed under the peak gate current condition-the median time-to-fail was dramatically reduced while the dispersion in the failure data was increased as plasma damage increased. Interface trap dominated hot carrier degradation-as in n-MOSFET's stressed under the peak substrate current condition or p-MOSFET's stressed at V/sub gs/=V/sub ds/-was not affected by plasma damage. Then both electron trapping and interface trap generation impact hot carrier degradation-as in n-MOSFET's stressed at V/sub gs/=V/sub ds/-plasma damage had a measurable but smaller effect on the failure statistics. These results are explained in terms of the differing impact of thermal annealing on bulk and interface traps. Finally, we show that reduced damage processes can mitigate the impact of plasma damage on MOSFET hot carrier robustness.<>

Fully-depleted Silicon-On-Insulator (SOI) MOSFETs are a strong potential candidate for future ULSI CMOS applications. In order to evaluate the merits of these devices an accurate model of the output characteristics applicable to sub-half micron channel lengths is needed. Previous work on modeling the I-V (current-voltage) characteristics of thin-film SOI MOSFETs has mainly been based on inaccurate velocity-field relation for carriers in the channel region. Moreover, in most models, conductance and capacitances show discontinuities at the transition points from subthreshold to saturation to linear regions. In this paper we report a physically based continuous analytical model for SOI MOSFETs that is represented by a single drain current equation valid in all regions of device operation ofinterest

Capacitive coupling and charge redistribution effects in product circuits can result in large V/sub ds/ overshoots which cause much larger reductions in n-MOSFET hot carrier failure times than the transition time dependencies previously studied. Using a variety of simulations, we show that these effects can occur in typical high performance microprocessor circuits. Controlling these effects and verifying circuit compliance are key to ensuring hot carrier robust circuit design. Although we focus on n-MOSFET's a symmetrical argument can be made for p-MOSFET's.<>

A simple methodology to accurately extract constant temperature model parameters from static measurements of fully-depleted SOI MOSFET current-voltage characteristics is demonstrated. Self-heating is included in an existing physically-based, short-channel bulk MOSFET model, PCIM, by allowing the temperature to change linearly with power dissipation at each bias point. Only a simple modification of the channel bulk charge in PCIM is necessary to adapt it for SOI. The temperature dependence of the physical parameters (mobility, flatband voltage, and saturation velocity) are also fitted and included in the model. Excellent fit to experimental fully-depleted SOI data is shown over a large range of bias conditions and channel lengths. Once the static SOI data is fitted, the constant temperature model parameters appropriate for circuit simulation are easily extracted.< >

Damage in surface channel p-MOS transistors arising from hot-carrier stress is examined using a recently proposed lifetime extraction method. It is shown that the p-MOS behavior with respect to hot-carrier stress runs counter to that of n-MOS transistors in many respects and has to be considered separately. Not only are the well-known post-stress gains in drive current obtained for p-MOS transistors, but also the measurement of the I-V characteristics with the stress damage at the source and drain ends shows opposite effects to n-MOS devices. The reasons for this are explained in terms of Coulombic screening by the channel charge. Stressing transistors in inverter-like and pass transistor-like modes are also discussed, and it is found that p-MOS transistors are much more sensitive to pass transistor-like damage than n-channel devices, due to increased channel length shortening in the pass transistor mode. It is shown that whereas at long gate lengths (> 0.5 mum) the degradation is limited to drain current changes, at shorter channel lengths (<0.5 mum), significant threshold voltage shifts arise. It is concluded that the reliability of p-channel transistors will become an important issue in the deep-submicrometer gate length regime.

The effects of reoxidation conditions on the hot-carrier properties of reoxidized nitrided oxides (RNOs) for both n- and p-MOS transistors are examined. Using a recently developed lifetime extraction technique for p-MOS transistors, it is shown that the reoxidation conditions for the RNO dielectric involve a compromise between n-channel hot-carrier hardness and p-channel hot-carrier susceptibility. Whereas the n-MOS transistor lifetimes are relatively unchanged as a function of reoxidation time, the p-MOS devices show monotonic increases with increased reoxidation time. This is attributed to changes of nitrogen concentration in the bulk of the oxide, but not at the interface. It is concluded that attention will have to be paid to the p-channel transistor reliability when optimizing the RNO process.<>