In this work we present how an empirical compact model can be constructed directly from current measurement data by employing a machine learning technique. We demonstrate our approach on emerging dual-gated reconfigurable device test structures, which have been fabricated directly on an industrial 22 nm process. Variability of key figures of merit in reconfigurable field effect transistor test structures in the early development stage is analysed. The resulting model enables a fast adaptation to new geometries and provides simulation speed and convergence properties of a compact model, while being also flexibly adaptable to new technological iterations, thus speeding-up development cycles.

Reconfigurable transistors are a new emerging type of device, which offer the promise to improve the resistance of electronic components against know-how theft. In order to enable a product development of such an emerging device, a cross-layer design enablement strategy is needed, as emerging technologies are not necessarily compatible withstandard tools used in the industry. In ‘CirroStrato’, we aim on the development of such a complete flow enabling CMOS co-integration of reconfigurable transistors, ranging from process adjustments, device modeling, library characterization, physical and logical synthesis up towards sophisticated hardware security tests. In this multi-partner-project (MPP) paper, our aim is to elucidate the overall design enablement flow, as well as current research challenges on the individual stages.

A major reliability concern in modern high-k field effect transistors (FETs) resembles the defect density distribution within the hafnium oxide layer as well as its interaction with the interfacial oxide layer. For a deeper understanding of the distribution of charged traps both energetically as well as spatially, it is essential to upgrade from a two level charge pumping scheme to a three level scheme. Through variation in pulse width and amplitude of a subsequent second level pulse, defect energy and location can be extracted inside the gate stack, which is important to understand the overall reliability impact of these traps onto the device properties.

HfO2-based ferroelectric FETs (FeFETs) offer excellent retention, scalability, and memory window. However, achieving high endurance is still challenging. Here, a fluorination treatment is presented that enables significant endurance and device stability improvement. Noise and charge pumping methods are applied to obtain deeper understanding of the underlying defect interaction in FeFETs.

Here we present a highly scalable reconfigurable field effect transistor concept, which is capable of dynamically switching between p-type, n-type, and ambipolar operation modes by adaptively changing the applied back-bias. The devices are processed on full-scale 300 mm wafers and reach gate lengths down to 20 mn, integrable into a 22 nm FDSOI platform with only minor process.modifications. We demonstrate symmetric IV characteristics of p-and n-program with I-ON/I-OFF ratio up to 10(3) at a V(DD )of 0.8 V, and propose an exploitation in hardware security. hi ambipolar mode, frequency multiplication requiring only a single transistor is experimentally demonstrated.

Highlights from Silicon Device Physics, material sciences and electrical engineering are among the first results to be presented from GFs subcontracts in the IPCEI-project, namely a reconfigurable FET compatible with 22-FDX-technology, a CMOS compatible new material Si doped HfO2 for electrocaloric/ pyroelectric effects on chip, modelling of the 22FDX devices in the higher GHz range and first 5G Dual Band transceiver blocks designed in 22FDX

The ferroelectric properties and crystal structure of doped HfO2 thin films were investigated for different thicknesses, electrode materials, and annealing conditions. Metal-ferroelectric-metal capacitors containing Gd:HfO2 showed no reduction of the polarization within the studied thickness range, in contrast to hafnia films with other dopants. A qualitative model describing the influence of basic process parameters on the crystal structure of HfO2 was proposed. The influence of different structural parameters on the field cycling behavior was examined. This revealed the wake-up effect in doped HfO2 to be dominated by interface induced effects, rather than a field induced phase transition. TaN electrodes were shown to considerably enhance the stabilization of the ferroelectric phase in HfO2 compared to TiN electrodes, yielding a Pr of up to 35 μC/cm2. This effect was attributed to the interface oxidation of the electrodes during annealing, resulting in a different density of oxygen vacancies in the Gd:HfO2 films. Ab initio simulations confirmed the influence of oxygen vacancies on the phase stability of ferroelectric HfO2.

The origin of the defects associated with the nitridation of the interface layer between Si and HfO2 is investigated. The electronic properties change upon nitridation which impact severely the gate capacitance and gate leakage current. We modeled the temperature-dependent leakage current in SiON/HfO2 gate dielectrics for positive and negative gate voltages by means of a multi-phonon trap-assisted tunneling scheme to extract the trap distribution. The results are supported by charge pumping measurements and simulation. To clarify the origin of the additional traps in the SiON interface we performed ab-initio calculation and correlated the results with the gate leakage current measurements. Finally, we shed new light on the relation between stress-induced leakage current and positive bias temperature instability.