Hafnia thin films are known to demonstrate excellent performance with strong ferroelectricity and high scalability, making them promising candidates for CMOS-compatible materials. However, the reliability of ferroelectric devices must be further improved. This study developed a Hf1-xZrxO2 ferroelectric capacitor with a nanolaminate structure that operated at remarkably low voltages, demonstrating excellent retention (>10 years/85 degrees C) and endurance (>10(10) cycles). The exceptional performance is attributed to the presence of thin tetragonal phase layers within the thick ferroelectric layers, which decreased the switching barrier in the nanolaminate films. Further, we verified phase crystallization via a detailed analysis of high-resolution transmission electron microscopy images. The improved switching propagation in the nanolaminate films was confirmed through switching speed measurements and theoretical models. Furthermore, we addressed pinching issues by precisely controlling the Hf/Zr ratio and O-3 treatment. The initial imprint and retention characteristics were improved by interfacial engineering. Moreover, by reducing the thickness, we have achieved reliable operation at 1.0 V with a 5.5 nm-thick device while maintaining high retention and endurance. This study is a significant step toward the realization of the longstanding problem of ferroelectric random access memory operation voltage with respect to endurance and retention characteristics.

Ferroelectric memory technology has again moved into the focus of academic and industrial R&D due to the discovery of ferroelectricity in HfO 2 . This paper gives an overview of FRAM-type as well as FeFET-type memory cells with particular focus on integrating ferroelectric capacitors (FeCAPs) in the Back-End-of-Line (BEoL) of a semiconductor manufacturing process. For FRAM memory cells, different capacitor types and integration schemes are described as well as considerations for access transistors and high-density implementations are discussed. For FeFET memory cells, advanced node floating gate memory cells with BEoL integrated FeCAPs are presented, and also back-gate approaches are reviewed.

In this study, we provide an insight into the polarization switching behavior of HfO2-based ferroelectric field-effect transistors (FeFETs) by utilizing the Landau-Ginzburg-Devonshire model in the multiscale physics-based modeling platform Ginestra (TM). Simulation results showed that a sufficient trap density is needed for complete polarization reversal. After that, we characterize the charge-trapping behavior with a dedicated experiment. The test results are then compared with the simulation results under the same test condition. The charge trapping behavior is more sensitive to applied voltage amplitude than to the pulse width. From the simulation, we could also see that the potential difference between the applied gate voltage and the channel potential at the onset of strong inversion remains constant for all gate voltages.

With the emergence of ferroelectric HfO2- and ZrO2-based thin films, the topic of ferroelectric memories has been experiencing a renaissance. These novel ferroelectric materials promise to overcome fundamental scaling and integration roadblocks of the three basic types of ferroelectric memory concepts, FRAM, FeFET and FTJs. While the understanding of the formation of ferro- and antiferroelectric properties in HfO2- and ZrO2 has matured in recent years, also new memory concepts have been suggested. Some represent an advancement of the three basic ferroelectric memories other enhance the performance of existing mainstream memories by incorporating (anti-)ferroelectric layers. The present work gives an overview of these different concepts. The CMOS compatibility allows for a large variety of device architectures, which can address the entire spectrum from mass storage to chache memory. There is a serious industry drive with demonstrators up to array level and most concepts are remarkably close to commercial state-of-the-art memories. Therefore, it seems that ferroelectric memory is finally poised to make inroads into mass markets.

Here we present a highly scalable reconfigurable field effect transistor concept, which is capable of dynamically switching between p-type, n-type, and ambipolar operation modes by adaptively changing the applied back-bias. The devices are processed on full-scale 300 mm wafers and reach gate lengths down to 20 mn, integrable into a 22 nm FDSOI platform with only minor process.modifications. We demonstrate symmetric IV characteristics of p-and n-program with I-ON/I-OFF ratio up to 10(3) at a V(DD )of 0.8 V, and propose an exploitation in hardware security. hi ambipolar mode, frequency multiplication requiring only a single transistor is experimentally demonstrated.

The difference in the switching behavior of program and erase operation in hafnium oxide based ferroelectric FETs (FeFETs) highlights insufficiency of models solely based on the ferroelectric hysteresis. In this work, program and erase characteristics across various FeFET dimensions have been compared in order to investigate the scaling-dependent switching behavior. A simulation model comprising the FeFET channel size, effective grain size, phase and orientation was developed to mimic the field controlled switching of ferroelectric grains and their effect on resulting current percolation paths. Finally, the impact of FET channel length L and width W was systematically analyzed both experimentally and using the developed model for both memory states. Investigations show how systematic W and L scaling can be utilized to tune switching behavior from abrupt digital-like, suitable for robust memory applications, to gradual analog-like, favorable in neuromorphic applications.

In this paper, recent advances on the development of Hafnium oxide (HfO2)-based ferroelectric field-effect transistors (FeFETs) are shown with respect to its memory window, trapping behavior and endurance characteristics. Although this novel ferroelectric memory cell shows superior characteristics such as device scalability, CMOS compatibility, fast access time and low power operation, the challenges for HfO2-based FeFET device lie with device variability and endurance. To investigate endurance failure in relation to charge trapping, different time delays were introduced to allow for detrapping of charges leading to improved endurance behavior. Besides the continuous improvements in process technology which minimize trap densities, we here demonstrate a mitigation of device variability, using a targeted programming scheme, with which a significantly lower device variability is achieved.

The ferroelectric HfO 2 based field effect transistor (FeFET) has been under research for many years and shows unique properties for applications in the field of emerging memories and in-memory computing. This work for the first time demonstrates how a target programming algorithm can improve the FeFET device characteristics with respect to endurance performance and variability for small device geometries. With this technique the threshold voltage V t of the memory cell can be targeted to any desired value, which is essential for multilevel cells and analog in-memory computing as used in AI accelerators. The switching, trapping and detrapping characteristics of the cell and their influence on the target programming algorithm are presented. The trapping and leakage characteristics are modelled using the Ginestra TM simulation software to extract the trap distribution in ferroelectric HfO 2 . Finally, a model for the underlying mechanism of the endurance degradation is proposed.

With the discovery of ferroelectricity in HfO 2 based thin films and the co-integration of ferroelectric field effect transistors (FeFET) into standard high-k metal gate (HKMG) CMOS platforms, the FeFET has emerged from a theoretical dream to an applicable reality. This paper summarizes the status of GLOBALFOUNDRIES FeFET technology and some of its potential applications. We show excellent 0.12µm 2 SRAM yields of our mature 28nm CMOS platform, with co-integrated FeFETs, exhibiting a solid memory window of 1.4V. In contrast to conventional embedded memory cells, the FeFET can be integrated like a regular 26Å EOT transistor, exhibiting two reversibly programmable VT states, while offering full design flexibility. We show state of the art across wafer VT variability of the programmed and erased states of the FeFETs and discuss its layout-dependence. Embedded size-competitive FeFETs already allow solid separation of the memory states, approaching a mature 6Sigma distribution. Reasonable endurance and stable data retention are demonstrated. Moreover, an outlook of this technology beyond the von Neumann computing will be discussed, considering some of the various applications of this new, versatile device.

Long data retention is a critical requirement for many of the potential applications of HfO2-based ferroelectric field-effect transistors (FeFETs). However, methods for its rapid assessment are still missing. In this article, we report a detailed investigation of the retention and switching properties of FeFETs fabricated in the 28-nm high- ${k}$ metal gate technology. We identify a clear correlation between the two properties and propose a method for fast prediction of the device retention behavior, which can be easily adopted to judge different fabrication processes. Finally, we extend the validity of the method to a direct assessment of disturb-free operating conditions, which may be particularly valuable for FeFET array operation.

In this paper, recent advances on the development of Hafnium oxide (HfO2)-based ferroelectric field-effect transistors (FeFETs) are shown with respect to its memory window, trapping behavior and endurance characteristics. Although this novel ferroelectric memory cell shows superior characteristics such as device scalability, CMOS compatibility, fast access time and low power operation, the challenges for HfO2-based FeFET device lie with device variability and endurance. To investigate endurance failure in relation to charge trapping, different time delays were introduced to allow for detrapping of charges leading to improved endurance behavior. Besides the continuous improvements in process technology which minimize trap densities, we here demonstrate a mitigation of device variability, using a targeted programming scheme, with which a significantly lower device variability is achieved.

Since the discovery of ferroelectricity in hafnium oxide, many development activities have been started worldwide to elaborate on its suitability for memory applications. This work summarizes and suggests ferroelectric hafnium oxide-based (FE-HfO2) memory technologies that could serve as a replacement for or addition to numerous spaces in the existing memory hierarchy. We discuss the use of ferroelectric field effect transistors (FeFET) for Cache memory up to its utilization as mass storage memory cell. The current shortcomings of the existing memory technologies are highlighted and the challenges for memory concepts based on FE-HfO2 are discussed. In total, the work illustrates that due to the fact that HfO2 has been established as the de facto standard high-k material in industry, the discovered ferroelectric properties in that same material might impact the existing memory landscape as a whole.

We show the implementation of a ferroelectric field effect transistor (FeFET) based eNVM solution into a leading edge 22nm FDSOI CMOS technology. Memory windows of 1.5 V are demonstrated in aggressively scaled FeFET cells with an area as small as 0.025 μm 2 At this point program/erase endurance cycles up to 10 5 are supported. Complex pattern are written into 32 MBit arrays using ultrafast program/erase pulses in a 10 ns range at 4.2 V. High temperature retention up to 300 °C is achieved. It makes FeFET based eNVM a viable choice for overall low-cost and low-power IoT applications in 22nm and beyond technology nodes.

The recent discovery of ferroelectricity in thin hafnium oxide films has led to a resurgence of interest in ferroelectric memory devices. Although both experimental and theoretical studies on this new ferroelectric system have been undertaken, much remains to be unveiled regarding its domain landscape and switching kinetics. Here we demonstrate that the switching of single domains can be directly observed in ultrascaled ferroelectric field effect transistors. Using models of ferroelectric domain nucleation we explain the time, field and temperature dependence of polarization reversal. A simple stochastic model is proposed as well, relating nucleation processes to the observed statistical switching behavior. Our results suggest novel opportunities for hafnium oxide based ferroelectrics in nonvolatile memory devices.

A compact nanoscale device emulating the functionality of biological synapses is an essential element for neuromorphic systems. Here we present for the first time a synapse based on a single ferroelectric FET (FeFET) integrated in a 28nm HKMG technology, having hafnium oxide as the ferroelectric and a resistive element in series. The gradual and non-volatile ferroelectric switching is exploited to mimic the synaptic weight. We demonstrate both the spike-timing dependent plasticity (STDP) and the signal transmission and discuss the effect of the spike properties and circuit design on STDP.

The discovery of ferroelectric properties of binary oxides revitalized the interest in ferroelectrics and bridged the scaling gap between the state-of-the-art semiconductor technology and ferroelectric memories. However, before hitting the markets, the origin of ferroelectricity and in-depth studies of device characteristics are needed. Establishing a correlation between the performance of the device and underlying physical mechanisms is the first step toward understanding the device and engineering guidelines for a novel, superior device. Therefore, in this paper a holistic modeling approaches which lead to a better understanding of ferroelectric memories based on hafnium and zirconium oxide is addressed. Starting from describing the stabilization of the ferroelectric phase within the binary oxides via physical modeling the physical mechanisms of the ferroelectric devices are reviewed. Besides, limitations and modeling of the multilevel operation and switching kinetics of ultimately scaled devices as well as the necessity for Landau-Khalatnikov approach are discussed. Furthermore, a device-level model of ferroelectric memory devices that can be used to study the array implementation and their operational schemes are addressed. Finally, a circuit model of the ferroelectric memory device is presented and potential further applications of ferroelectric devices are outlined.

We successfully implemented a one-transistor (1T) ferroelectric field effect transistor (FeFET) eNVM into a 28nm gate-first super low power (28SLP) CMOS technology platform using two additional structural masks. The electrical baseline properties remain the same for the FeFET integration and the JTAG-controlled 64 kbit memory shows clearly separated states. High temperature retention up to 250 °C is demonstrated and endurance up to 105 cycles was achieved. The FeFET unique properties make it the best candidate for eNVM solutions in sub-2x technologies for low-cost IoT applications.

ABSTRACT With the discovery of ferroelectric hafnium oxide (FE-HfO2), the ferroelectric field effect transistor (FeFET), a long-term contender for non-volatile data storage, has finally managed to scale to the 2× nm technology node. Here for the first time, we correlate the thickness dependent ferroelectric properties of Si:HfO2 with the memory characteristics of small (56 bit) FeFET arrays. First, an electrical and structural analysis of metal-ferroelectric-metal capacitors is given. Even though possessing room-temperature deposited top electrodes, TiN / Si:HfO2 (20 nm) / TiN capacitors are showing deteriorated polarization characteristics as compared to their 10 nm Si:HfO2 counterparts. This could be attributed to an increased monoclinic phase fraction, as indicated by small-signal capacitance voltage and grazing incidence X-ray diffraction measurements. Identical Si:HfO2 thin films with thicknesses of 10 nm and 20 nm respectively, were utilized in a 28 nm high-k metal-gate CMOS flow to form small FeFET memory arrays of AND architecture. After extracting the most suitable operating conditions from erase matrix, single cell evaluation was performed by standard VP/3 program and a novel VP/3 positive-source drain erase scheme. Array cells incorporating 10 nm Si:HfO2 films showed a maximum memory window of 1.03 V whereas cells incorporating 20 nm Si:HfO2 films could reach up to 1.57 V. Moreover, in accordance to the basic material properties, the previously observed increased monoclinic phase fraction in 20 nm Si:HfO2 thin films correlate well with a reduced number of functional FeFET cells.

In this paper potential strategies to overcome the endurance limitations of hafnium oxide based ferroelectric field effect transistors are discussed. These pathways are based on the assumption that the high interfacial field stress and the accompanying charge injection in the metal-ferroelectric-insulator-semiconductor gate stack are the dominant degradation mechanisms during program and erase operation. Three different approaches capable of lowering or eliminating the interfacial field stress are being assessed - lowering the electrical field stress induced by polarization reversal; utilizing low voltage sub-loop operation; altering the capacitive divider within the gate stack.