Thin, flexible packaging of integrated circuits (ICs) is essential for next-generation implantable devices, where extreme miniaturisation must be achieved without compromising reliability. This work presents a fabrication process for ultrathin chip packages based on liquid crystal polymer (LCP), selected for its biocompatibility, chemical stability, and barrier properties. Dies thinned to 30 μ m were embedded into laser-skived cavities within a high- and low-temperature LCP stack using vacuum lamination. Electrical access was achieved using a hybrid picosecond-laser and reactive ion etching (RIE) via process, followed by metallisation and fan-out patterning. The approach was validated using PTCE daisy-chain structures and MSP430 microcontrollers. Across 11.704 vias, all were electrically functional with negligible resistance contribution. Of 16 encapsulated MSP430 devices, 62.5% remained programmable. Assembly on flexible substrates yielded high pad-level connectivity (96.8% PTCE, 99.1% MSP430) and 75% functional yield. Full LCP encapsulation was demonstrated as a proof of concept, confirming the feasibility of this scalable ultrathin packaging approach.

High-Density Interconnect (HDI) printed circuit boards (PCBs) rely on stacked and staggered microvias to achieve compact, high-performance interconnects. However, the thermo-mechanical reliability of these microvias remains a critical concern due to cyclic stresses induced by mismatched coefficients of thermal expansion (CTE) between copper and dielectric materials. This study investigates the strain behavior of multilevel microvia configurations using finite element analysis (FEA) under reflow thermal cycling from 20 °C to 230 °C. A unit-cell modeling approach is employed to simulate various microvia offsets relative to a core via, ranging from fully stacked to fully staggered arrangements. Results reveal that partially overlapped microvias particularly those offset by ±100 μm exhibit the highest strain concentrations, exceeding those in fully stacked configurations. These key offsets occur when microvias with a top diameter of 150 μm and a bottom diameter of 100 μm partially overlap, causing increased stress at their interface. These findings highlight the detrimental impact of misregistration-induced partial overlaps and underscore the importance of avoiding overlap in staggered designs. Ongoing thermal cycling experiments on HDI test coupons are being conducted to validate the simulation results through cross-sectional failure analysis. The study provides actionable insights for optimizing microvia placement to enhance the reliability of HDI PCBs in high-performance applications.

This study comprehensively examines the barrier properties, aging behavior, and failure mechanisms of Parylene F-VT4 films, applied at four distinct thicknesses (0.3 µm, 0.6 µm, 0.9 µm, and 1.2 µm), as encapsulation layers for implantable medical devices. Parylene F-VT4, a fluorinated polymer known for its mechanical flexibility, thermal stability, and chemical inertness, is a promising candidate for long-term hermetic encapsulation. Parylene F-VT4 was uniformly deposited via a dedicated chemical vapor deposition (CVD) process typically used for Parylene depositions. The investigation of the Parylene F-VT4 films included pinhole density characterization, electrochemical impedance spectroscopy (EIS), and testing of coating lifetime based on the resistance of Cu meanders protected by Parylene F-VT4 when immersed in phosphate-buffered saline (PBS) under accelerated aging conditions (PBS at 60 °C) over 550 days. The EIS results demonstrated that thicker coatings (1.2 µm) exhibited excellent barrier properties and resistance to electrolyte penetration, whereas thinner coatings (0.3 µm and 0.6 µm) showed more rapid degradation due to microvoids and pinholes. The temporal evaluation of EIS spectra highlighted the gradual decrease in impedance magnitude, indicating the ingress of ions and water into the coating. The lifetime in PBS at 60 °C was determined by resistance-based lifetime measurements on Cu meander structures coated with Parylene F-VT4 coatings. The lifetime at 37 °C was calculated, assuming an acceleration factor of 2 per 10 °C increase in temperature, yielding lifetimes of approximately 25 days, 6.4 months, 2.3 years, and 4.5 years for 0.3 µm, 0.6 µm, 0.9 µm, and 1.2 µm coatings, respectively. These findings highlight the critical relationship between thickness and durability, providing valuable insights into the long-term performance of thin Parylene F-VT4 films for implantable devices.

The motivation of this work is to enable the use of piezoelectric micromachined ultrasonic transducer (PMUT)-based implants within the human body for biomedical applications, particularly for power and data transfer for implanted medical devices. To protect surrounding tissue and ensure PMUT functionality over time, biocompatible and hermetic encapsulation is essential. This study investigates the impact of Parylene F-VT4 layers of various thicknesses as well as the effect of multilayer stacks of Parylene F-VT4 combined with atomic layer-deposited nanolayers of Al2O3 and HfO2 on the mechanical and acoustic properties of PMUTs. PMUTs with various diameters (40 µm, 60 µm, and 80 µm) are fabricated and tested both as stand-alone devices and as arrays. The mechanical behavior of single stand-alone PMUT devices is characterized in air and in water using laser Doppler vibrometry (LDV), while the acoustic output of arrays is evaluated by pressure measurements in water. Experimental results reveal a non-monotonic change in resonance frequency as a function of increasing encapsulation thickness due to the competing effects of added mass and increased stiffness. The performance of PMUT arrays is clearly influenced by the encapsulation. For certain array designs, the encapsulation significantly improved the arrays’ pressure output, a change that is attributed to the change in the acoustic wavelength and inter-element coupling. These findings highlight the impact of encapsulation in modifying and potentially enhancing PMUT performance.

Embedding flexible electronic circuits into a sustainable polymer is an emerging and significant topic in the field of in-mold electronics (IME). Ensuring strong adhesion between the flexible circuit and the molded polymer is critical for the durability of IME products. In this study, three different types of etched copper polyimide (PI) foils were used as the substrate of electronic components. Two bio-based and biodegradable polymers of polylactic acid (PLA) and polyhydroxybutyrate (PHB) served as the overmolding material. Four different surface pretreatments: drying, polydopamine (PDA) coating, PDA coating followed by thermal treatment under vacuum, oxygen plasma, and 3-aminopropyltriethoxysilane (APTES) were applied to the PI surface prior to the overmolding process to investigate the influence on the adhesive strength. Additionally, a thermoplastic polyurethane (TPU) adhesive layer was introduced via vacuum lamination to further improve adhesion. The main objective of this study was to evaluate the adhesive strength between etched PI and overmolded biopolymers before and after surface modifications. The loci of failure were analyzed using scanning electron microscopy (SEM). The results indicate that laminated TPU is the most effective approach for improving adhesion between polyimide foils and biopolymers.

This study presents a novel approach to manufacture a rigid printed circuit board (PCB) using sustainable polymers. Current PCBs use a fossil-fuel-based substrate, like FR4. This presents recycling challenges due to its composite nature. Replacing the substrate with an environmentally friendly alternative leads to a reduction in negative impacts. Polylactic acid (PLA) and Polyhydroxybutyrate (PHB) biopolymers are used in this study. These two biopolymers have low melting points (130–180 °C, and 170–180 °C, respectively) and cannot withstand the high temperature soldering process (up to 260 °C for standard SAC (SnAgCu, tin/silver/copper) lead free solder processes). Our approach for replacing the PCB substrate is applying the PLA/PHB carrier substrate at the end of the PCB manufacturing process using injection molding technology. This approach involves all the standard PCB processes, including wet etching of the Cu conductors, and component assembly with SAC solder on a thin flexible polyimide (PI) foil with patterned Cu conductors and then overmolding the biopolymer onto the foil to create a rigid base. This study demonstrates the functionality of two test circuits fabricated using this method. In addition, we evaluated the adhesion between the biopolymer and PI to achieve a durable PCB. Moreover, we performed two different end-of-life approaches (debonding and composting) as a part of the end-of-life consideration. By incorporating biodegradable materials into PCB standard manufacturing, the CO2 emissions and energy consumption are significantly reduced, and installation costs are lowered.

This paper presents the feasibility of using polylactic acid polymer as the overmolding material in in-mold electronics (IME). IME represents a technology integrating flexible electronic circuits into plastics in the molding process. This approach reduces weight and material consumption and simplifies the process. The increasing applications and consumption of these products result in a growing problem of electronic waste (ewaste). This necessitates a transition towards eco-friendly in-mold electronics and responsible end-of-life solutions. Currently, the most widely used plastic in this industry is polycarbonate both as flexible substrate and molding material. This polymer is derived from petroleum-based sources. This contributes to the depletion of non-renewable sources and greenhouse gas emissions. By using biopolymers as molding material, we can potentially minimize the environmental impact associated with this type of e-waste. Polylactic acid (PLA) is a bio-based and biodegradable polymer derived from renewable plant sources. In this study, polylactic acid is used only as the overmolding material. Typically, in IME the flexible circuit is fabricated using printed electronic (PE) technology. However, due to challenges regarding the stability of assembled electronic components, a polyimide-copper (PI/Cu) flex circuit fabricated through conventional printed circuit boards (PCB) manufacturing line is used in this paper. The goal of this work is to investigate if the PLA can be separated from the flexible circuit as end-of-life strategy. The debonding strategy simplifies the reuse, refurbish, or recycle of each separated layer. The IME technology was validated by showing the functionality of two different types of test circuits to demonstrate proof of concept. The adhesive strength between flex foil and PLA was evaluated by the 180 degrees peel test method. At the end-of-life, the debonding of PLA and flex circuit is investigated. In review, this research focuses on optimizing the overmolding process for PLA, exploring the compatibility of the PLA molding with the functionality of electronic components, and assessing the end-of-life practice for IME.

This study reports on the encapsulation of piezoelectric micromachined ultrasonic transducer (PMUT) devices by hermetic Parylene F-VT4 (PVT4) and multilayer stacks of PVT4 combined with atomic layer deposition films. These encapsulations are evaluated for their potential to enable implantable PMUT devices for biomedical applications, providing necessary protection for both the device and the patient while preserving device performance. The mechanical and acoustic properties of coated and uncoated single PMUTs and 64x64 PMUT arrays were characterized in water. Results indicate that the resonance frequencies of both the single elements and the arrays change non-monotonically with increasing PVT4 thickness due to alterations in the equivalent mechanical properties of the composite membrane. While single PMUTs exhibited a monotonic decrease in displacement, encapsulation significantly improved the array's pressure output, attributed to changes in acoustic wavelength and inter-element coupling. This enhancement underscores the effectiveness of encapsulation in optimizing overall performance.

The European Space Agency (ESA) in collaboration with its industrial partners has been updating their standards for Printed Circuit Board (PCB) design, qualification and procurement. These standards include design margin to mitigate the risks of latent short-circuit and open-circuit failures, as well as new test and inspection methods for qualification and for lot conformance, such as temperature humidity bias test, conductive anodic filament test, interconnect stress test and dark-field microscopy. The test methods are used to benchmark technology from ESA-qualified PCB manufacturers, and to qualify high-density interconnect (HDI) technology including microvias. To investigate the reliability of the advanced manufacturing methods, various traditional and accelerated thermal stress tests are performed on two and three layers of staggered and stacked microvia configurations, as well as the thermo-mechanical modelling of stress factors. This paper describes the motivation for the updated standards, the benchmarking of novel test methods and first reliability data on advanced HDI technology.

A cost-effective, compact, and high-performance antenna element for beamforming applications in all fifth-generation (5G) New Radio bands in the [24.25–29.5]$ \,$GHz spectrum is proposed in this letter. The novel antenna topology adopts a square patch, an edge-plated air-filled cavity, and an hourglass-shaped aperture-coupled feed to achieve a very high efficiency over a wide frequency band in a compact footprint ($\boldsymbol{{0.48} \lambda _0 \times \text{0.48}\lambda _0}$). Its compliance with standard printed circuit board (PCB) fabrication technology, without complex multilayer PCB stack, ensures low-cost fabrication. The antenna feedplane offers a platform for compact integration of active electronic circuitry. Two different modular 1 $ \boldsymbol{\times }$ 4 antenna arrays were realized to demonstrate its suitability for broadband multiantenna systems. Measurements of the fabricated antenna element and the antenna array prototypes revealed a $-$10 dB impedance bandwidth of 7.15 GHz (26.8%) and 8.2 GHz (30.83%), respectively. The stand-alone antenna features a stable peak gain of 7.4$ \,\pm \,$0.6$ \,$dBi in the [24.25–29.5]$ \,$GHz band and a measured total efficiency of at least 85%. The 1 × 4 array provides a peak gain of 10.1$ \,\pm \,$0.7$ \,$dBi and enables grating-lobe-free beamsteering from ${-}\text{50}^\circ$ to $ \text{50}^\circ$.

High density interconnect (HDI) printed circuit boards (PCBs) and associated assemblies are essential to allow space projects to benefit from the ever increasing complexity and functionality of modern integrated circuits such as field programmable gate arrays (FPGAs), digital signal processors (DSPs) and application processors. Increasing demands for functionality translate into higher signal speeds combined with an increasing number of I/Os. To limit the overall package size, the contact pad pitch of the components is reduced. The combination of a high number of I/Os with a reduced pitch places additional demands onto the PCB, requiring the use of laser drilled microvias, high aspect ratio core vias and small track width and spacing. While the associated advanced manufacturing processes have been widely used in commercial, automotive, medical and military applications; reconciling these advancements in capability with the reliability requirements for space remains a challenge. This paper provides an overview of the ongoing ESA project on high-density PCB assemblies, led by imec with the aid of ACB and Thales Alenia Space in Belgium. The goal of the project is to design, evaluate and qualify HDI PCBs that are capable of providing a platform for assembly and the routing of small pitch AAD for space projects. Two categories of HDI technology are considered: two levels of staggered microvias (basic HDI) and (up to) three levels of stacked microvias (complex HDI). In this paper, the qualification of the basic HDI technology in accordance with ECSS-Q-ST-70-60C is described. The results of the thermal cycling, interconnection stress testing (IST) and conductive anodic filament (CAF) testing are provided. The test vehicle design and test parameters for each test method are discussed in detail. Introduction Two main drivers are commonly identified for HDI PCBs: (1) the small pitch and high number of I/Os of key components and (2) the increasing performance of these components resulting in high-speed signal lines on the boards. The use of microvias allows to reduce the length of the signal path, improving both signal integrity and power integrity. Critical nets may suffer from crosstalk due to the dense routing within the fanout. The routing of differential pairs in between the pins of a 1.0 mm pitch component requires fine line widths and spacing. Differential pair routing in between the buried vias for 0.8 mm pitch components is no longer possible. The pairs need to be split within the fanout area and the effect on signal integrity will depend on the length of the split. The change in width on single-ended nets, as well as a change in the spacing and/or trace widths of a differential pair will cause an impedance discontinuity. Choosing the appropriate layer build-up and via types will thus improve both route-ability and signal integrity. An important consideration in the definition of technology parameters for HDI PCBs is that component pitch and the number of I/Os cannot be addressed independently. A high pin count component (> 1000 pins) with 1.0 mm pitch can require the use of microvias to reduce the total layer count or to improve the shielding of controlled impedance lines. On the other hand, the escape routing of a 0.5 mm pitch component with only two rows of solder balls can be performed without microvias and fine line widths and spacing. Increasing the layer count to be able to route one or more high pin count components will result in an increase in PCB thickness, which impacts the minimum via drill diameter through limitations on the via aspect ratio and thus again restricts routing possibilities. In order to define the HDI technology parameters, the specifications of area array devices (AADs) used in past, present and future space projects need to be known. Looking into the complex components for space that are currently under development, the ceramic column grid array (CCGA) with a pitch of 1.0 mm will remain the package of choice for the coming years. This is, for example, the case for the new Xilinx FPGA (RT-ZU19EG: CCGA1752) [1], the CNES VT65 telecom ASIC (CCGA1752) [2] and ESA’s Next Generation Microprocessor (NGMP, CCGA625) [3]. Column grid arrays with smaller pitch (0.8 mm) have been demonstrated in R&D [4], although no commercial implementations have been found. As originally published in the SMTA Proceedings

The use of electronic microsystems as medical implants gains interests due to the combination of superior device functionality with extreme miniaturization. Electronic devices are not biocompatible and will suffer from corrosion, hence a very good hermetic device encapsulation is of utmost importance. The hermetic sealing of implantable electronics requires extremely good bi-directional barrier properties against diffusion of water, ions and gases. Moreover, extremely long biostability against body fluids and biomolecules is an important requirement for the barrier materials. In this work, an ALD multilayer of AlOx and HfOx in combination with flexible polyimide is used as a flexible hermetic encapsulation of an electronic CMOS chip which serves as an implantable probe (so called hd TIME (active high-density transverse intrafascicular microelectrode) probe) for neural recording and stimulation [1]. The main part consists of a 35μm thin CMOS chips with electrodes on top encapsulated with alternating layers of spin coated polyimide (PI2611) and biocompatible ALD layers. The total encapsulation is developed to provide excellent barrier properties. Each ALD stack (ALD-3) consists of AlOx (20 nm) capped on both sides with HfOx (8 nm) to avoid hydrolysis of AlOx. The ALD deposition temperature is 250°C. Special attention is payed to the adhesion of the ALD layers toward polyimide and vice versa. 3 to 4 PI/ALD-3 dyads are used for the total encapsulation, since long term implantation of the medical device is envisaged. Testing however is done using only a part of the total encapsulation, in order to enable to learn about the barrier properties in a reasonnable timeframe. The WVTR of a PI/ALD-3/PI film reached a value of 2.1 10-5 g/m2day (38°C and 100% RH), the total encapsulation with 3 to 4 dyads will lead to WVTR’s in the order of 10-6g/m2day. The same PI/ALD-3/PI film has been deposited on structured copper meanders and is exposed to PBS at 60°C for 3.5 years (equivalent to 17.5 years at 37°C) [2]. Up till now, no change in Cu resistivity has been observed proving the excellent barrier properties of the PI/ALD-3/PI film. [1] Rik Verplancke et al., 2020 J. Micromech. Microeng., 30, 015010 [2] Changzheng Li et al. 2019 Coatings, 9, 579

Barrier layers for the long-term encapsulation of implantable medical devices play a crucial role in the devices’ performance and reliability. Typically, to understand the stability and predict the lifetime of barriers (therefore, the implantable devices), the device is subjected to accelerated testing at higher temperatures compared to its service parameters. Nevertheless, at high temperatures, reaction and degradation mechanisms might be different, resulting in false accelerated test results. In this study, the maximum valid temperatures for the accelerated testing of two barrier layers were investigated: atomic layer deposited (ALD) Al2O3 and stacked ALD HfO2/Al2O3/HfO2, hereinafter referred to as ALD-3. The in-house developed standard barrier performance test is based on continuous electrical resistance monitoring and microscopic inspection of Cu patterns covered with the barrier and immersed in phosphate buffered saline (PBS) at temperatures up to 95 °C. The results demonstrate the valid temperature window to perform temperature acceleration tests. In addition, the optimized ALD layer in combination with polyimide (polyimide/ALD-3/polyimide) works as effective barrier at 60 °C for 1215 days, suggesting the potential applicability to the encapsulation of long-term implants.

Despite its introduction over 3 decades ago, designing, manufacturing and testing of high-density interconnect (HDI) printed circuit boards (PCBs) remains a topic of discussion. A plethora of advanced manufacturing processes is used to realize HDI PCBs in general and microvias in particular. The introduction of HDI technology for space applications and the pursuit for qualification by the European Space Agency create the need for a critical review of existing test methods. Two categories of HDI technology are considered: two levels of staggered microvias (basic HDI) and three levels of semi-stacked microvias (complex HDI). Several challenges were encountered during the design, testing and evaluation of the basic HDI technology. The main issues were related to the positioning of the microvias with respect to the core via, interconnection stress testing (IST) coupon design, microvia failures and core via performance. ESA has gained significant heritage with interconnection stress testing. IST parameters for mechanical vias and microvias are defined in the current European Cooperation for Space Standardization (ECSS) standard for PCBs. Especially for microvias, recent experiences with failures have led to a revision of the test method. Alternatives microvia test methods as convection reflow assembly simulation and current-induced thermal cycling (CITC) are explored in this study. A thorough understanding of the impact of design variables, manufacturing processes and test parameters is vital for meaningful microvia testing.

In recent years, there has been an increased interest in soft packaging for non-rigid medical implants. A promising technique to realize reliable soft packaging involves the inclusion of thin layers of atomic layer deposited (ALD) ceramics between biocompatible polymer layers. Crucial requirements are that those ALD layers are biocompatible and pinhole free to prevent unwanted interactions between the implant and the human body. In this research, a biocompatible thermally deposited 20 nm thick Al2O3-ALD layer is investigated for porosity by using three different techniques: copper electroplating, copper wet etching and linear sweep voltammetry (LSV). The porosity values obtained with the copper electroplating and copper wet etching techniques are comparable with one another (3.14 x 10(-6)%-3.18 x 10(-7)%) but are four to five orders of magnitude smaller than the porosity estimation obtained by the LSV test (8.04 x 10(-2)%-3.23 x 10(-3)%). This divergence in porosity is explained by two different contributions leading to an overestimation of pinhole density obtained through LSV. The destructive character of the LSV technique during which additional current contributions arise from copper corrosion and pinhole enlargement is identified as a first factor contributing to an overestimation of pinhole distribution. A second contribution arises from Poole-Frenkel emission and trap-assisted tunneling through the insulating Al2O3-ALD layer. As a consequence, LSV does not only detect pinholes but also single point defects, cluster defects and sealed line defects originating from unreacted OH ligands during ALD deposition. Based on those findings it was concluded that copper wet etching is the preferred method to be used in pinhole detection.

Within our internal FITEP technology platform (FITEP: Flexible Implantable Thin Electronic Package), a novel implantable packaging technology is under development in order to realize a very small, flexible, biomimetic package for electronic implants. This new platform enables a radical miniaturization of the final implanted device, which opens many new possibilities for the medical world, since it will be possible to insert electronic sensors in very small locations, such as arteries, nerves, glands,... The device encapsulation consists of a multilayer of biocompatible polymers and ultrathin ceramic diffusion barriers deposited using ALD techniques (ALD: atomic layer deposition) in order to fabricate a very thin and flexible but also highly hermetic device packaging. Concerning the selection of biocompatible polymers, polyimide can offer a profound mechanical support for the various device components, while Parylene with its excellent step coverage creates a highly conformal coating surrounding all components. Hermeticity can be realized by the use of ultrathin ceramic ALD layers such as Al2O3 and HfO2. An optimized ALD process will result in layers from very high quality with very good step coverage. As such, selected ALD layers of only a few tens of nm thick, can exhibit very low Water Vapor Transmission Rates (WVTR), making these ALD materials ideal as ultrathin diffusion barriers. The tested polyimide/ALD stack proved to be a very hermetic enclosure: copper patterns protected with the polyimide/ALD stack are still in perfect condition after more than 2 years of immersion in saline at 60 °C (test is still ongoing), while Cu patterns protected by the polyimide stack without ALD barriers showed first signs of damage already after 6 weeks exposure to saline. Platinum and gold are best suited for metallization of implanted electronics, but these noble metals do not adhere easily to polymers, hence dedicated measures to promote metal-polymer adhesion are essential. The FITEP platform is applied on a Si-probe for implantation in the peripheral nerves, consisting of a CMOS chip with recording and stimulation electrodes [Op de Beeck, M. 2017]. The chip is thinned down to 35um and packaged using polyimide and ALD multi-stacks, resulting in a 75um thin fully encapsulated chip, optimized to reduce the Foreign Body Reaction to obtain optimum electrode-nerve contact. Flexible interconnects are fabricated using gold and platinum sandwiched between polymers and ALD layers. For optimal charge injection, iridium oxide is used as electrode material. After this hermetic FITEP-based chip encapsulation, the CMOS chip is still fully functional, which was tested dry (in air) as well as during submersion in saline. First acute in vivo stimulation tests have shown good electrode stimulation capabilities. Mechanical bending tests on long 5um thick gold interconnects are performed, showing that even after up to 1.5 million bending cycles, no cracks occurred in the gold patterns (testing in air). Longer term immersion in saline and in-vivo testing showed some problems related to loss of adhesion and to galvanic effects of the metallization. These observations were leading to some improvements in the fabrication of the encapsulation. In a second packaging iteration of the CMOS chip, these improvements were realized and a new series of encapsulated devices is fabricated. First results are promising, showing improved metal adhesion. Longer term stability tests are on its way.

Long-term packaging of miniaturized, flexible implantable medical devices is essential for the next generation of medical devices. Polymer materials that are biocompatible and flexible have attracted extensive interest for the packaging of implantable medical devices, however realizing these devices with long-term hermeticity up to several years remains a great challenge. Here, polyimide (PI) based hermetic encapsulation was greatly improved by atomic layer deposition (ALD) of a nanoscale-thin, biocompatible sandwich stack of HfO2/Al2O3/HfO2 (ALD-3) between two polyimide layers. A thin copper film covered with a PI/ALD-3/PI barrier maintained excellent electrochemical performance over 1028 days (2.8 years) during acceleration tests at 60 °C in phosphate buffered saline solution (PBS). This stability is equivalent to approximately 14 years at 37 °C. The coatings were monitored in situ through electrochemical impedance spectroscopy (EIS), were inspected by microscope, and were further analyzed using equivalent circuit modeling. The failure mode of ALD Al2O3, ALD-3, and PI soaking in PBS is discussed. Encapsulation using ultrathin ALD-3 combined with PI for the packaging of implantable medical devices is robust at the acceleration temperature condition for more than 2.8 years, showing that it has great potential as reliable packaging for long-term implantable devices.

A novel dual-band substrate-integrated waveguide (SIW) antenna array topology is proposed for operation in the 28 and 38 GHz frequency bands. Four miniaturized quarter-mode SIW cavities are tightly coupled, causing mode bifurcation, and yielding an antenna topology with four distinct resonance frequencies. A pair of resonances is assigned to both the 28 and 38 GHz band, achieving wideband operation in both frequency ranges. Moreover, owing to the exploited miniaturization technique, an extremely compact array topology is obtained, facilitating easy and straightforward integration. The computer-aided design process yields a four-element antenna array that entirely covers the 28 GHz band (27.5-29.5 GHz) and 38 GHz band (37.0-38.6 GHz) with a measured impedance bandwidth of 3.65 and 2.19 GHz, respectively. A measured broadside gain of 10.1 dBi, a radiation efficiency of 75.75% and a 3 dB beamwidth of 25 degrees are achieved in the 28 GHz band. Moreover, in the 38 GHz band, the measured broadside gain amounts to 10.2 dBi, a radiation efficiency of 70.65% is achieved, and the 3 dB beamwidth is 20 degrees.

In this work, the development of an active high-density transverse intrafascicular micro-electrode (hd-TIME) probe to interface with the peripheral nervous system is presented. The TIME approach is combined with an active probe chip, resulting in improved selectivity and excellent signal-to-noise ratio. The integrated multiplexing capabilities reduce the number of external electrical connections and facilitate the positioning of the probe during implantation, as the most interesting electrodes of the electrode array can be selected after implantation. The probe chip is packaged using thin-film manufacturing techniques to allow for a minimally invasive electronic package. Special attention is paid to the miniaturization, the mechanical flexibility and the hermetic encapsulation of the device. A customized probe chip was designed and packaged using a flexible, implantable thin electronic package (FITEP) process platform. The platform is specifically developed for making slim, ultra-compliant, implantable complementary metal-oxide-semiconductor based electronic devices. Multilayer stacks of polyimide films and HfO2/Al2O3/HfO2 layers deposited via atomic layer deposition act as bidirectional diffusion barriers and are key to the hermetic encapsulation. Their efficacy was demonstrated both by water vapor transmission rate tests and accelerated immersion tests in phosphate buffered saline at 60 degrees C. Using the hd-TIME probe, an innovative implantation method is developed to prevent the fascicles from moving away when the epineurium is pierced. In addition, by transversally implanting the hd-TIME probe in the proximal sciatic nerve of a rat, selective activation within the nerve was demonstrated. The FITEP process platform can be applied to a broader range of integrated circuits and can be considered as an enabler for other biomedical applications.

This paper demonstrates a D-band transition between a coplanar waveguide line and a rectangular dielectric waveguide> The transition uses an intermediate metallic wave guide partially implemented on printed circuit board (PCB) to enhance the coupling efficiency and to offer a solid assembly base. The transition was designed to convert the CPW mode to the El, mode in a dielectric rectangular waveguide. In this paper we present the design, fabrication and measurement data, showing a 7 dB measured insertion loss for a back-to-back transition connected by a 80 mm long section of polystyrene, measured with GSG on-wafer probes.