We investigate the occurrence of single-event transient (SET) in the programmable logic (PL) of a 16-nm fin field-effect transistor (FinFET) system-on-chip (SoC) using single-photon absorption (SPA) laser testing. Results indicate sensitive locations decorrelated from configuration random access memory (CRAM) errors and a significant difference between SET and single-event upset (SEU) thresholds. The correlation of these observations with available heavy ion results on the same technology is discussed. Technology computer-aided design (TCAD) simulation results of SET in a single inverter are presented. Implications for SET rate prediction are discussed.

The single-event latch-up (SEL) cross section of a 16 nm bulk finFET programmable system-on-chip (SoC) is investigated by combining single-photon absorption (SPA) laser testing, emission microscopy (EMMI), and embedded instrumentation. The contributions of different SEL-sensitive areas identified by their current increase, light emission, and functional signatures are measured. The effect of temperature and IO bias is evaluated. The laser results show an excellent correlation with heavy ion data and delimit the origin of SEL in this device by excluding the occurrence of SEL in the core logic for this technology.

EV10AS940 is a 10-bit single channel Analog-toDigital Converter (ADC) capable of Ka-band operation, enabling a sampling rate up to 12.8GSps, with power consumption no more than 2.5W. The EV10AS940 is packaged with an organic substrate to allow high speed and high bandwidth operations. This paper presents the results of TID tests carried out in 2023 to validate its adaptation to a harsh space environment. The measurements were carried out at TRAD (Labège, France) using the GAMRAY irradiation facility. The parts have received a total dose of 100krad at a dose rate of 325 rad/h. After irradiation, the annealing procedure was followed. Throughout the test, the main parameters of the device were measured with a test bench. The measurements involved monitoring power consumption as well as ENOB, SNR, THD and SFDR parameters for different input powers. The results show that the device behaved perfectly throughout the test, with no significant variations. This campaign proves the chip is perfectly suited for the long duration space applications.

EV10AS940 is a high-performance single channel, 10bit, 12.8GSps Analog-to-Digital Converter (ADC) that allows sampling of signals up to the Ka-band. The high analog input bandwidth (32GHz) makes the EV10AS940 the best candidate to address RF direct sampling architectures, as it allows optimizing the signal chain by eliminating the need to integrate a dedicated mixer. this paper presents the results of SEE tests performed at RADEF (RADiation Effects Facility, at Jyväskyla in Finland) on June 1st 2023. The ADC was put through heavy ions testing with five different ion energies. The goal of this test was to measure the sensibility of the device for Single Event Latch-up (SEL), Single Event Functional Interrupt (SEFI) and Single Event Upset (SEU). SEFI and SEU testing were performed with two different input signals, SIN and RAMP mode. Particular attention was paid to SEFI resolution, and different scenarios were tested during the campaign to identify the best response.

This paper submits a proof of concept of an injection-locked Phase-Locked-Loop (PLL) in 180 nm CMOS technology. The target data rate is 1.6 Gbps with a supply voltage of 1.8 V. The architecture is based on an injection-locked ring oscillator implemented in a PLL that helps improving the oscillator jitter and thus the phase noise. In addition, a fully symmetrical XOR gate as phase detector allows to get a low phase noise while simplifying the design. This circuit achieves a phase noise of -119.1 dBc/Hz at 1 MHz and a jitter of 0.6 mUI with a reference frequency of 1.6 GHz. Post-layout simulation results show a PLL locking time with injection at 1.6 GHz of 20 ns while consuming 41.4 mW.

This paper reports on the different responses observed during heavy ion irradiation and Total Ionizing dose test on a newly developed Rad-Hard, 8-Channel, 50ksps to 1Msps, 12-Bit A/D Converter, called RHFAD128.

We present Single Event Effects characterization and Total Ionizing Dose behaviour up to 300 krad(Si) on Rad-Hardened A/D converter.

A clock and data recovery (CDR) circuit dedicated to satellite embedded high-speed data links is implemented in a 0.13 mum CMOS technology. Its radiation hardening is obtained thanks to an innovative architecture based on an injection-locked oscillator (ILO) associated with a phase-alignment circuit. Its low single-event transient (SET) sensitivity is shown thanks to heavy-ion and laser testing.

This paper presents the results of the study on commercial components identification and evaluation in naturally radiation hardened technologies.

This paper presents heavy ion single event effect as well as total ionising dose test results for candidate spacecraft electronics. Microelectronics selected and tested include Logic families and Line Interfaces.