Analyzing image content usually comes at the expense of a power consumption incompatible with battery-powered systems. Aiming at proposing a solution to this problem, this paper presents an imager with full on-chip object recognition, consuming sub-10μW using standard 4T pixels in 90nm imaging CMOS technology, opening the path for both wake-up and high-quality imaging. It combines multi-modality event-of-interest detection with self-controlled capabilities, a key for low-power applications. It embeds a log-domain auto-exposure algorithm to increase on-chip automation. The power consumption figures range from 3.0 to 5.7μW at 5fps for a QQVGA resolution while enabling background subtraction and single-scale object recognition. This typically shows a measured 94% accuracy for a face detection use case.

This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip.

This paper presents a 2-layer 3D stacked Back Side Illuminated vision chip performing high speed programmable parallel computing by exploiting in-focal-plane pixel readout circuits. The proposed circuit exhibits a 5500fps frame rate, 5 times higher than previous works without reducing ADC resolution. It allows heterogeneous parallel computations on up to 31×31 inter-pixels neighborhoods in a single chip.

A CMOS burst image sensor reaching 5Mfps with 52 frames in-pixel digital memory has been designed and tested. It fully takes advantage of 3D stacked technology to implement a scalable architecture for 8-bits quantization and data storage at pixel level in CMOS technology. This imager also benefits from backside illumination (BSI) for improved fill factor and wide spectrum sensitivity. A demonstrator has been fabricated, embedding two types of 3D based pixel. In this paper we present the very first experimental test results of 3D stacked in-pixel digital burst image sensor. These results show advantages of using 3D technology to obtain a very high frame rate with both relaxed design conditions and readout timing constraint compared to conventional high speed burst image sensors.

This paper describes a 3D Integrated Circuit (3DIC) architecture of a burst image sensor (BIS) with embedded digitization and digital storage. This architecture also proposes a new technique to further increase both the frame rate and the stored image capacity at the cost of a spatial resolution reduction. A 2D monolithic demonstrator that takes into account the constraints of a future 3D-IC imager has been fabricated. Experimental results are presented showing that a frame rate from 5 up to 45 Mega frames per second can be achieved. This fully functional approach paves the way to the very first in-focal-plane digital BIS.

The Laboratoire Electronique et Traitement de l’Information (LETI) of the Commissariat à l’Energie Atomique (CEA, Grenoble, France) has been involved in the development of infrared detectors based on HgCdTe (MCT) material for over 30 years, mainly for defence and security programs [1]. Once the building blocks are developed at LETI (MCT material process, diode technology, hybridization, …), the industrialization is performed at SOFRADIR (also in Grenoble, France) which also has its own R&D program [2]. In past years, LETI also developed infrared detectors for space astrophysics in the mid infrared range – the long wave detector of the ISOCAM camera onboard ISO – as well as in the far infrared range – the bolometer arrays of the Herschel/PACS photometer unit –, both instruments which were under the responsibility of the Astrophysics department of CEA (IRFU/SAp, Saclay, France). Nowadays, the infrared detectors used in space and ground based astronomical instruments all come from vendors in the US. For programmatic reasons – increase the number of available vendors, decrease the cost, mitigate possible export regulations, …– as well as political ones – spend european money in Europe –, the European Space Agency (ESA) defined two roadmaps (one in the NIR-SWIR range, one in the MWIR-LWIR range) that will eventually allow for the procurement of infrared detectors for space astrophysics within Europe. The French Space Agency (CNES) also started the same sort of roadmaps, as part of its contribution to the different space missions which involve delivery of instruments by French laboratories. It is important to note that some of the developments foreseen in these roadmaps also apply to Earth Observations. One of the main goal of the ESA and CNES roadmaps is to reduce the level of dark current in MCT devices at all wavelengths. The objective is to use the detectors at the highest temperature where the noise induced by the dark current stays compatible with the photon noise, as the detector operating temperature has a very strong impact at system level. A consequence of reaching low levels of dark current is the need for very low noise readout circuits. CEA and SOFRADIR are involved in a number of activities that have already started in this framework. CEA/LETI does the development of the photo-voltaic (PV) layers – MCT material growth, diode technologies–, as well as some electro-optical characterisation at wafer, diode and hybrid component levels, and CEA/IRFU/SAp does all the electro-optical characterisation involving very low flux measurements (mostly dark current measurements). Depending of the program, SOFRADIR can also participate in the development of the hybrid components, for instance the very low noise readout circuits (ROIC) can be developed either at SOFRADIR or at CEA/LETI. Depending of the component specifications, the MCT epitaxy can be either liquid phase (LPE, which is the standard at SOFRADIR for production purposes) or molecular beam (MBE), the diode technology can be n/p (standard at LETI and SOFRADIR) or p/n (under development for several years now) [3], and the input stage of the ROIC can be Source Follower per Detector (SFD for very low flux low noise programs) or Capacitive Trans Impedance Amplifier (CTIA for intermediate flux programs) [4]. This paper will present the different developments and results obtained so far in the two NIR-SWIR and MWIR-LWIR spectral ranges, as well as the perspectives for the near future. CEA/LETI is also involved in the development of MCT Avalanche Photo Diodes (APD) that will be discussed in other papers [5,6].

CEA and SOFRADIR have been manufacturing and characterizing near infrared detectors in the frame of ESA's Near Infrared Large Format Sensor Array roadmap to develop a 2Kx2K large format low flux low noise device for space applications such as astrophysics. These detectors use HgCdTe as the absorbing material and p/n diode technology. The technological developments (photovoltaic technology, readout circuit, ...) are shared between CEA/LETI and SOFRADIR, both in Grenoble, while most of the performances are evaluated at CEA/IRFU in Saclay where a dedicated test facility has been developed, in particular to measure very low dark currents. The paper will present the current status of these developments at the end of ESA's NIRLFSA phase 2. The performances of the latest batch of devices meet or are very close to all the requirements (quantum efficiency, dark current, cross talk, readout noise, ...) even though a glow induced by the ROIC prevents the accurate measurement of the dark current. The current devices are fairly small, 640x512 15 mu m pixels, and the next phase of activity will target the development of a full size 2Kx2K detector. From the design and development, to the manufacturing and finally the testing, that type of detector requests a high level of mastering. An appropriate manufacturing and process chain compatible with such a size is needed at industrial level and results obtained with CEA technology coupled with Sofradir industrial experience and work on large dimension detector allow French actors to be confident to address this type of future missions.

This paper presents recent developments at Commissariat à l’Energie atomique, Laboratoire d’Electronique et de Technologie de l’Information infrared laboratory on processing and characterization of p-on-n HgCdTe (MCT) planar infrared focal plane arrays (FPAs) in short-wave infrared (SWIR) spectral band for the astrophysics applications. These FPAs have been grown using both liquid phase epitaxy and molecular beam epitaxy on a lattice-matched CdZnTe substrate. This technology exhibits lower dark current and lower series resistance in comparison with n-on-p vacancy-doped architecture and is well adapted for low flux detection or high operating temperature. This architecture has been evaluated for space applications in long-wave infrared and very-long-wave infrared spectral bands with cut-off wavelengths from 10 μm up to 17 μm at 78 K and is now evaluated for the SWIR range. The metallurgical nature of the absorbing layer is also examined and both molecular beam epitaxy and liquid phase epitaxy have been investigated. Electro-optical characterizations have been performed on individual photodiodes from test arrays, whereas dark current investigation has been performed with a fully functional readout integrated circuit dedicated to low flux operations.

Ultra High Speed (UHS) imaging is at the forefront of the imaging technology for some years now. These image sensors are used to shoot high speed phenomenon that require about hundred images at Mega frame-per-seconds such as detonics, plasma forming, laser ablation… At such speed the data read-out is a bottleneck and CMOS and CCD image sensors store a limited number of frames (burst) on-chip before a slow read-out. Moreover in recent years 3D integration has made significant progresses in term of interconnection density. It appears as a key technology for the future of UHS imaging as it allows a highly parallel integration, shorter interconnects and an increase of the fill factor. In the past we proposed an idea of 3D integrated burst image sensor with on-chip A/D conversion that overcome the state of the art in term of frame-per-burst. This sensor is made of 3 stacked layers respectively performing the signal conditioning, the A/D conversion and the burst storage. We present here different solutions to implement the analogue front-end of the first layer. We will describe three circuits for three purposes (high frame rate, power efficiency and sensitivity). To support our point, we provide simulation results. All these front-ends perform global shutter acquisition.

Infrared detection is widely used in astrophysics and plays a key role in several space missions aiming for example at scanning the sky to discover new objects (coolest stars, dust-obscured galaxies, exo-planets …) or studying the evolution of the universe, where light is redshifted in the infrared range. In many cases the space telescope involves an HgCdTe infrared detector operating at low frame rate over long integration time. Due to the very low input signal, dark current and readout noise are essential figures that must be minimized to get the best detector sensitivity. This kind of application also requires very large focal plane array (FPA) often relying on a butting arrangement of large detectors. The trend is to increase the single detector format from 1Kx1K to 2Kx2K and 4Kx4K. For very large formats, material quality and detector process may affect the production yield and the global infrared FPA cost. As a result the detector format could result from a trade-off taking into account producibility.

A THz 31×31 pixel, 100 fps image sensor integrated in a 130 nm CMOS process is presented. Taking advantage of the possibility to modulate the active source that lights the scene, a significant improvement in sensitivity and NEP is achieved by shifting the modulated THz radiation, by means of an antenna/MOSFET, then filtering the signal band using an in-pixel 16-paths passive SC-filter combined with a CT Gm-C filter resulting in a high Q factor of 100. This THz imager features a measured NEP of 533 pW at 270 GHz and 732 pW at 600 GHz respectively, and a sensitive readout chain with an input referred noise of 0.2 μVRMS.

CEA-Leti has developed a monolithic large focal plane array bolometric technology optimized for 2D real-time imaging in the terahertz range. Each pixel consists in a silicon microbolometer coupled to specific antennas and a resonant quarter-wavelength cavity. First prototypes of imaging arrays have been designed and manufactured for optimized sensing in the 1-3.5THz range where THz quantum cascade lasers are delivering high optical power. NEP in the order of 1 pW/sqrt(Hz) has been assessed at 2.5 THz. This paper reports the steps of this development, starting from the pixel level, to an array associated monolithically to its CMOS ROIC and finally a stand-alone camera. For each step, modeling, technological prototyping and experimental characterizations are presented.

In this paper we present a new asynchronous readout technique designed for a single element infrared detector (SWIR HgCdTe APD). This circuit aims to perform photon counting on a hybridized detector at a cryogenic temperature for an atmospheric LIDAR (LIght Detection And Ranging) application. Accordingly, for the most important specifications, we obtain a very low input referred noise generated by the circuit ~100 μVrms ↔ 12 e- rms. Also, a bandwidth of 0.5GHz is achieved in order to satisfy the most demanding needs. The circuit architecture, the simulation bench and results are included and illustrated in this paper.

It is well known that 3D integration technology brings a lot to image sensors in term of fill-factor and in-situ processing. As 3D stacking allows massively parallel processing, it looks like an effective way to store the image close to the pixel in burst image sensor. This paper discusses two new 3D stacked architectures for burst high speed imaging with in-situ A/D conversion, one with analog memories, the other based on digital storage. We propose appraisals of frame-rate, memory depth and power consumption for both architectures. Thanks to this assessment, analog storage architecture appears as a good way to reach unmatched speed performances (>10Terapixel/s) while digital storage architecture seems an interesting solution to reach high memory depth (>200 frames). Moreover, this study identifies a very high power consumption of the digital and analog storage architectures during the image capture.

In this paper, we present the design of the MWIR channels of EChO. Two channels cover the 5-11 micron spectral range. The choice of the boundaries of each channel is a trade-off driven by the science goals (spectral features of key molecules) and several parameters such as the common optics design, the dichroic plates design, the optical materials characteristics, the detector cut-off wavelength. We also will emphasize the role of the detectors choice that drives the thermal and mechanical designs and the cooling strategy.

Three-dimensional (3-D) flash light detection and ranging (LADAR) imaging is based on time of flight (TOF) measurement of a single laser pulse. The laser pulse coming back from the observed object will be detected only if the number of photons received by each pixel generates a signal greater than the pixel noise. In order to extract this weak photonic signal from the noise we use the high gain and low excess noise of the HgCdTe avalanche photodiode (APD) arrays developed at CEA/LETI. The sensor consists of a 30-mu m pitch APD detector array hybridized to a 320 x 256 pixels ROIC for passive and active imaging. In passive mode the focal plane array behaves like a thermal imager and we measured 30 mK of noise-equivalent temperature difference. In active imaging mode, each pixel sensed the time of flight and the intensity two-dimensional (2-D) of a single laser pulse. Laboratory tests show a range noise of 11 cm for 4300 photoelectrons per pixel and detection limit under 100 photoelectrons. The sensor was also used during a field trial to record 2-D and 3-D real-time videos. The quality of the images obtained demonstrates the maturity of HgCdTe-APD-array technology. (C) 2012 Society of Photo-Optical Instrumentation Engineers (SPIE). [DOI: 10.1117/1.OE.51.6.061305]

Proportional photon detection has been demonstrated using linear mode HgCdTe avalanche photodiodes (APDs) hybridized on a specially designed read-out integrated circuit (ROIC). The ROIC was designed to detect photons at a moderate bandwidth (10 MHz) with a low noise of 10 electrons per characteristics time of the ROIC and to be compatible with large area-small pixel focal plane array (FPA) applications. Proportional photon counting was demonstrated by reproducing the Poisson statics for average photon number states ranging between m=0.8 to 8 photons, at low to moderate avalanche gains M=40-200, using both mid-wave infrared (MWIR) and (short-wave infrared) SWIR HgCdTe APDs. The probability distribution function of the gain was estimated from the analysis of the amplitude of detected residual thermal photons in the MWIR APDs. The corresponding probability distribution functions was characterized by a low excess noise factor F and high asymmetry which favours a high photon detection efficiency (PDE), even at high threshold values. An internal PDE of 90 % was estimated at a threshold level of 40 % of the average signal for a single photon. The dark count rate (DCR) was limited by residual thermal photons in the MWIR APD to about 1 MHz. A geometrical and spectral filtering of this contribution is important to achieve the ultimate performance with MWIR detectors. In this case, the DCR was estimated by interpolation to about 8 kHz. The SWIR HgCdTe APD device had a lower residual photon flux (60 kHz), but was found to be limited by tunnelling dark current noise at high gains at a rate of 100 kHz.

A new readout IC (ROIC) with a 2 step A/D conversion for cooled infrared image sensors is presented in this paper. The sensor operates at a 50Hz frame rate in an Integrate-While-Read snapshot mode. The 16 bit ADC resolution preserves the excellent detector SNR at full well (~3Ge-). The ROIC, featuring a 320×256 array with 30μm pixel pitch, has been designed in a standard 0.18μm CMOS technology. The IC has been hybridized (indium bump bonding) to a LWIR (Long Wave Infra Red) detector fabricated using our in-house HgCdTe process. The first measurement results of the detector assembly validate both the 2-step ADC concept and its circuit implementation. This work sets a new state-of-the-art SNR of 88dB.

Hybrid InGaAs focal plane arrays are very interesting for night vision because they can benefit from the nightglow emission in the Short Wave Infrared band. Through a collaboration between III-V Lab and CEA-Leti, a 640x512 InGaAs image sensor with 15 mu m pixel pitch has been developed.The good crystalline quality of the InGaAs detectors opens the door to low dark current (around 20nA/cm(2) at room temperature and -0.1V bias) as required for low light level imaging. In addition, the InP substrate can be removed to extend the detection range towards the visible spectrum.A custom readout IC (ROIC) has been designed in a standard CMOS 0.18 mu m technology. The pixel circuit is based on a capacitive transimpedance amplifier (CTIA) with two selectable charge-to-voltage conversion gains. Relying on a thorough noise analysis, this input stage has been optimized to deliver low-noise performance in high-gain mode with a reasonable concession on dynamic range. The exposure time can be maximized up to the frame period thanks to a rolling shutter approach. The frame rate can be up to 120fps or 60fps if the Correlated Double Sampling (CDS) capability of the circuit is enabled.The first results show that the CDS is effective at removing the very low frequency noise present on the reference voltage in our test setup. In this way, the measured total dark noise is around 90 electrons in high-gain mode for 8.3ms exposure time. It is mainly dominated by the dark shot noise for a detector temperature settling around 30 degrees C when not cooled. The readout noise measured with shorter exposure time is around 30 electrons for a dynamic range of 71dB in high-gain mode and 108 electrons for 79dB in low-gain mode.