Precise capacitor ratios are employed in a variety of analog and mixed signal integrated circuits. The use of identical unit capacitors to form larger capacitances can easily produce 1% accuracy, but, in many cases, 0.1% accuracy can provide important performance advantages. Unfortunately, the ultimate matching precision of the ratio is limited by a number of systematic and random error sources. We have analyzed the source and significance of the systematic error sources on actual integrated circuit layouts and isolated five key contributors. Based on this analysis, we have developed a list of generic layout rules and a layout scheme that predict matching accuracies better than 0.1% for the individual systematic error sources using capacitor sizes in the range of 20-40 /spl mu/m. >
Presented is a technique for implementing the functions of charge skimming and variable integration time in Schottky-barrier focal plane arrays (FPAs) that utilize a field plate. This technique requires only pulsing the field plate that lies over the diode and is currently DC biased to suppress diode edge leakage. Therefore, no additional structure is needed in the silicon substrate, and the basic readout clocking is unaffected. Any interline transfer FPA can benefit from this approach. Both qualitative theory and confirming experimental results are described.< >
A description is given of 128*128 and 256*256 pixel Schottky-barrier infrared focal-plane arrays that incorporate meander channel CCD readout structures for the IR-induced image charge. These innovations reduce the nonimaging area in each pixel and increase the fill factor. A design figure of merit that allows direct comparisons of design efficiency while normalizing pixel area, design rules, and ...
The fabrication and initial laboratory test of 128x128-element focal plane arrays integrating IrSi detectors with a cutoff wavelength of approximately 9.4 μm and surface-channel CCD readout circuitry are presented. This extends thermal imaging with silicide Schottky-barrier detector arrays into the long-wavelength infrared (LWIR) spectral band (8 to 14 μm) for the first time. High-quality imagery with a minimum resolvable temperature of approximately 0.3 K is obtained.
Platinum silicide (PtSi) on p-silicon Schottky-barrier focal plane arrays (FPAs) are strong candidates for infrared (IR) detection up to a wavelength of about 5 mu m. However, an inherently low quantum efficiency (about 1% at 4 mu m) makes it important to maximize the fill factor or the area of the array that is IR-sensitive. Current designs use an n/sup -/ guard ring around the PtSi diodes to suppress edge leakage. This is effective, but the guard-ring overlap can significantly reduce the sensitive area of the diode. An aluminium plate that is already used as a photon reflector above the diode in current designs can be positively biased as a field plate to create a surface depletion layer around the diode periphery. This produces leakage current suppression equivalent to the guard ring without giving up IR-sensitive diode area.< >
Scanning electron microscope (SEM) voltage contrast testing is being developed for functional design verification, failure analysis, and development of VLSI devices. This technique imparts little electrical loading and requires no physical contact to the chip, both of which are advantages for device testing via internal nodes. One area of concern, however, is the effect of the low-energy electrons (<5 keV) on the transistor parameters. Even for incident electrons below 8 keV which do not penetrate to the gate oxide, a threshold shift has been observed in SOS MOSFET's. The parameter shift is a result of damage to the gate oxide by secondary X-rays generated by the electrons. Limits on the electron energy and fluence are set to minimize the threshold shift during SEM testing. It is found that under the proper conditions sufficient time is available to perform both voltage contrast imaging and nodal waveform measurements without incurring serious threshold voltage shifts.
Buried channel charge coupled devices are particularly sensitive to the effects of bulk state impurities on such device characteristics as thermal leakage current, charge transfer efficiency, and noise. This paper reviews the statistics relevant to these effects and describes an improved application of the double pulse experiment for probing bulk impurities. This experiment found that the dominant impurity in our devices had an energy level 0.404 eV from one of the bandedges and determined a lower limit of 1013 cm−3 for the concentration. A close match with previously reported results suggests that this energy level is referenced to the valence band and represents iron. By eliminating the corrosive gas used to getter sodium in the thermal oxides, the source of iron was removed and the affected device characteristics improved about two orders of magnitude.
Buried channel CTD's must be designed to isolate their depleted channels from charge generated in the substrate by penetrating radiation to obtain optimum transient radiation hardness or radiation detector time response. This can be achieved by employing an NPN structure so that the electrons generated in the N substrate are confined by the reverse biased P-N junction from diffusing across the P l...
A simple closed-form mathematical model is derived for the time-limited spill mechanism in charge equilibration inputs on profiled peristaltic charge-transfer devices (CTD's). Two modes of operation, peak detection and signal sampling, are analyzed representing extremes in the time variation of the input signal relative to the CTD clock. The theoretical models indicate two linear regions of the input-output curve characterized by thermal-diffusion-dominated transport and self-induced drift-dominated transport, respectively. These linear regions are clearly visible in the experimental data. By drawing straight lines through these data, the necessary model parameters are easily derived and these, in turn, give physical quantities such as thermal diffusion coefficient and surface doping. The numbers obtained in this fashion are a good indication of the model's validity when compared to independent measurements. Additional verification is provided by the accurate prediction of the output versus spill time curve at a single input level based on the parameters obtained by matching the model to the experimental input-output curve for one spill time. Theoretical curves are presented to illustrate the dependence on input gate geometries and spill time. Finally, isolines of time-dependent nonlinearity are plotted versus input voltage and spill time to aid in locating the sufficiently linear operating region.
Lumped transmission line equivalent circuit models offer a proven technique for calculating small signal admittances of MOS capacitors. Typically, this is done by means of 6 × 6 matrix multiplications. Recently, however, we derived for the lossless MOSC a set of three differential equations which are easier and more convenient to solve than the more general matrix method.
Experimental capacitance-voltage (C-V) data are presented to verify recent theories of surface minority carrier redistribution in MOS capacitors biased near strong inversion. The surface layer of minority carriers shunts a portion of the surface space-charge layer resulting in a small capacitance minimum and a slightly larger asymptotic capacitance in strong inversion than predicted by older theory. The agreement between the experiment and the recent theory is very good. The experimental asymptotic capacitance in strong inversion is slightly larger than predicted. This discrepancy is attributable to the surface quantization effect not contained in the recent theory.
First order Ricatti equations are obtained for the capacitive 3-wire transmission line of a one-dimensional MOS capacitance which give an order of magnitude improvement in numerical computation time over the transmission matrix solution of the lumped section equivalent circuit model of the transmission line.
The commonly assumed linear model of surface potential fluctuation using a Gaussian distribution is shown to be invalid. A macrocapacitor model previously proposed by us is used to analyze the effects of spatially inhomogeneous oxide charge distribution on the MOS C-V characteristics at various rms oxide charge deviations and temperatures. It is shown that a Gaussian oxide charge distribution of rms value of as low as 1011 electrons/cm2 gives rise to a doubly peaked probability distribution of the surface potential fluctuation. Substantial errors in fast surface state density occur using either the low-frequency capacitance (Berglund), the high-frequency capacitance (Terman), or the temperature dependence (Gray-Brown) analysis of the fast surface states from C-V curves. A major source of error is in the value of the average surface potential which is changed substantially from the ideal case by the presence of inhomogeneous oxide charge distributions.
A simple and explicit formula is derived to give the oxide capacitance from MOS C-V data in the accumulation but nondegenerate range of surface potential. The effect of majority impurity deionization is shown to be unimportant due to a higher surface concentration of majority carriers than impurities in the accumulation range. A first-order correction is obtained to take into account the degenerate or Fermi statistics of the majority-carrier surface concentration for oxide capacitance determinations from C-V data in the strong accumulation and degenerate range of surface potentials.
It is demonstrated experimentally that the observed surface density of state peaks near the band edges, obtained from the Terman analysis of the capacitance−voltage characteristics of silicon MOS capacitors, can be attributed to areal inhomogeneities of oxide charges. An excellent quantitative match between theory and experiment is obtained after an extension of the theory of the C−V characteristics of inhomogeneous samples to include the real surface state densities.
The finite spatial extension of the inversion layer minority carriers shunts the dielectric capacitance of the inversion layer and increases the high frequency semiconductor surface space charge layer capacitance in the strong inversion range by about 5 per cent. This distributed minority carrier distribution also gives rise to a small (about 1 per cent) high frequency capacitance minimum near the onset of strong surface inversion. A simple two-lump model is developed which is accurate to within 0·4 per cent of the numerical solution obtained from the exact transmission line model. Applied gate voltages at the capacitance minimum are presented graphically as a function of oxide thickness with the substrate impurity concentration as a parameter. Surface quantization effect is not taken into account.
