Data and code working together is fundamental to machine learning (ML), but the context around datasets and interactions between datasets and code are in general captured only rudimentarily. Context such as how the dataset was prepared and created, what source data were used, what code was used in processing, how the dataset evolved, and where it has been used and reused can provide much insight, but this information is often poorly documented. That is unfortunate since it makes datasets into black-boxes with potentially hidden characteristics that have downstream consequences. We argue that making dataset preparation more accessible and dataset usage easier to record and document would have significant benefits for the ML community: it would allow for greater diversity in datasets by inviting modification to published sources, simplify use of alternative datasets and, in doing so, make results more transparent and robust, while allowing for all contributions to be adequately credited. We present a platform, Renku, designed to support and encourage such sustainable development and use of data, datasets, and code, and we demonstrate its benefits through a few illustrative projects which span the spectrum from dataset creation to dataset consumption and showcasing.

Emerging scale-out workloads need extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power, limiting further expansion and requiring improvements in the computational density per server and in the per-operation energy. Continuing to improve the computational resources of the cloud while staying within physical constraints mandates optimizing server efficiency. In this work, we demonstrate that modern server processors are highly inefficient for running cloud workloads. To address this problem, we investigate the microarchitectural behavior of scale-out workloads and present opportunities to enable specialized processor designs that closely match the needs of the cloud.

Emerging scale-out workloads require extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power, limiting further expansion and calling for improvements in the computational density per server and in the per-operation energy. Continuing to improve the computational resources of the cloud while staying within physical constraints mandates optimizing server efficiency to ensure that server hardware closely matches the needs of scale-out workloads.In this work, we introduce Cloud Suite, a benchmark suite of emerging scale-out workloads. We use performance counters on modern servers to study scale-out workloads, finding that today's predominant processor micro-architecture is inefficient for running these workloads. We find that inefficiency comes from the mismatch between the workload needs and modern processors, particularly in the organization of instruction and data memory systems and the processor core micro-architecture. Moreover, while today's predominant micro-architecture is inefficient when executing scale-out workloads, we find that continuing the current trends will further exacerbate the inefficiency in the future. In this work, we identify the key micro-architectural needs of scale-out workloads, calling for a change in the trajectory of server processors that would lead to improved computational density and power efficiency in data centers.

Emerging scale-out workloads require extensive amounts of computational resources. However, data centers using modern server hardware face physical constraints in space and power, limiting further expansion and calling for improvements in the computational density per server and in the per-operation energy. Continuing to improve the computational resources of the cloud while staying within physical constraints mandates optimizing server efficiency to ensure that server hardware closely matches the needs of scale-out workloads. In this work, we introduce CloudSuite, a benchmark suite of emerging scale-out workloads. We use performance counters on modern servers to study scale-out workloads, finding that today’s predominant processor microarchitecture is inefficient for running these workloads. We find that inefficiency comes from the mismatch between the workload needs and modern processors, particularly in the organization of instruction and data memory systems and the processor core microarchitecture. Moreover, while today’s predominant microarchitecture is inefficient when executing scale-out workloads, we find that continuing the current trends will further exacerbate the inefficiency in the future. In this work, we identify the key microarchitectural needs of scale-out workloads, calling for a change in the trajectory of server processors that would lead to improved computational density and power efficiency in data centers.

Chip-multiprocessors require a coherence directory to track data sharing and order accesses to the shared data. Scaling coherence directories to support a large number of cores is challenging due to excessive area requirements of the directories. The state-of-the-art proposals reduce the directory size by not keeping coherence information for private data. These approaches are useful for workloads that have predominantly private data, but are not applicable to workloads with shared data. We observe that data are not actively shared by multiple cores. In workloads with a shared dataset, although each core accesses the whole data, the chance that multiple cores access the same piece of data at the same time is low. Based on this observation we design a Spatiotemporal Coherence Tracking scheme that drastically reduces the directory size without sacrificing performance. The proposed directory scheme uses dual-grain tracking and switches between the granularities whenever possible to save the area. It dynamically detects spatial regions of data that are privately accessed by one core over a time period and for those regions, increases coherence tracking granularity from block-level to region-level. Our experimental results show that the proposed approach can reduce the baseline sparse directory size by at least 75% across a variety of commercial and scientific workloads, while sacrificing only 1% of performance. Using our approach, the directory can be under-provisioned to have fewer entries than the number of cache blocks that are being tracked.

This paper presents the comparison of two design methodologies applied to the design of a co-processor dedicated to image processing. The first methodology is the classical development based on specifying the architecture by directly writing a HDL model using VHDL or Verilog. The second methodology is based on specifying the architecture by using a high level dataflow language followed then by direct synthesis to HDL. The priciple of developing a dataflow description consists on defining a network of autonomous entities called actors, which can communicate only by sending and receiving data tokens. Each entity in the process of consuming and generating data tokens performs completely independent and concurrent processing. A heterogeneous platform composed by a SW processor and the designed HW co-processor is used to compare the results of the designs obtained by the two different methodologies. The comparison of the results shows that the implementations based on the dataflow methodology, not only can be completed with an important reduction of design and development time, but also enable efficient re-design iterations capable of achieving performances, which are comparable in efficiency to design obtained by hand written HDL.

In this paper, we propose a scan cell architecture that decreases power consumption and the total consumed energy. In the method, which is based on data compression, the test vector (TV) set is divided into two repeated and unrepeated partitions. The repeated part, which is common among some of the TVs, is not changed during the new scan path where the new TV will be filled. Therefore, every time that a new TV is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. As a result, the TV is applied to the CUT in a fewer number of clock cycles. In addition, the values of some scan cells remain unchanged leading to a lower switching activity in the scan-path during test mode. Besides, by latching the inputs of the CUT, the proposed scan chain architecture avoids transitioning of TVs into the circuit inputs at the time of shifting. This also saves system power during the test mode. Our architecture has been applied to ISCAS89 circuits. Simulation results reveal up to 66% reduction in the test power consumption when compared to the conventional scan-path architecture.

This paper presents an efficient method of implementing Taylor expansion diagrams (TED) which is called binary Taylor diagrams (BTD). BTD is based on Taylor series like TED, but uses a binary data structure. So BTD functions are simpler than those of TED.

Network buffers used in network devices, have to allow line-speed buffering of packets while they maintain a large number of queues. Due to the growing speed of network links and the increasing number of data queues, the design of network embedded systems operating at high speeds is often restricted by their memory subsystem performance. In this paper, we show architecture of a network buffer subsystem which efficiently manages storing and retrieving data packets of multi gigabit network lines among 16 K different queues. The proposed architecture is implemented in FPGA and uses available memory technologies. It is ideal to be used as a queue management component in network processors, switches, stream processors, or any other application which require high-performance queue management engines

This paper shows a novel scan-cell architecture that reduces both power consumption and the total consumed energy using a data compression technique. Based on the data compression methodology, the vector set is partitioned into two repeated and unrepeated segments. The repeated part, which is common among some of the vectors, is not changed during the new scan-path where new test vector is filled. This way, every time that a new test vector is applied to the circuit, only the cells of the scan-path which are not repeated are altered and other cells retain their values. This leads to a fewer number of clock cycles when the new test vector is applied to the circuit under test. The architecture proposed in this work has been applied to ISCAS89 circuits. Our simulation results show a reduction in the test power consumption up to about 70% when compared to the conventional scan-path architecture.