This paper describes the architecture and implementation of the original gaming-oriented synergistic processor element (SPE) in both 90-nm and 65-nm silicon-on-insulator (SOI) technology and introduces a new SPE implementation targeted for the high-performance computing community. The Cell Broadband Engine™ processor contains eight SPEs. The dual-issue, four-way single-instruction multiple-data processor is designed to achieve high performance per area and power and is optimized to process streaming data, simulate physical phenomena, and render objects digitally. Most aspects of data movement and instruction flow are controlled by software to improve the performance of the memory system and the core performance density. The SPE was designed as an 11-FO4 (fan-out-of-4-inverter-delay) processor using 20.9 million transistors within 14.8 mm 2 using the IBM 90-nm SOI low-k process. CMOS (complementary metal-oxide semiconductor) static gates implement the majority of the logic. Dynamic circuits are used in critical areas and occupy 19% of the non-static random access memory (SRAM) area. Instruction set architecture, microarchitecture, and physical implementation are tightly coupled to achieve a compact and power-efficient design. Correct operation has been observed at up to 5.6 GHz and 7.3 GHz, respectively, in 90-nm and 65-nm SOI technology.

This contribution presents a formatting method for encrypting a plaintext block using a block encryption algorithm (such as Elliptic Curve, RSA, DES, etc.) having a block size smaller than that of the plaintext block. The process of encrypting a plaintext block consists of first masking the plaintext block to form a masked plaintext block and then encrypting a portion or all of the masked plaintext block. The masking method is a reversible procedure which performs a “complete” mixing of the plaintext block such that no bit in the plaintext block can be determined unless every bit in the masked plaintext block is known. We recommend that the scheme presented in this contribution be adopted into the baseline text as a formatting scheme for encrypting a long plaintext block using a short-block encryption algorithm. _________________________________________ NOTICE: This contribution has been prepared to assist the IEEE P1363 standard body. This proposal is made by the authors as a basis of discussion. This contribution should not be construed as a binding proposal on the authors or their companies. Specifically, the authors and their companies reserve the right to amend or modify the statements contained herein. Φ This work was done while Don Johnson was working at IBM. Ψ Contact person Mohammad Peyravian Email: peyravn@vnet.ibm.com Phone: +1-919-254-7576

This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.