Ga 2 O 3 is a promising Wide-Band-Gap material for power electronics due to its large bandgap and inexpensive native substrate. However, due to technological difficulties, only normally-ON n-type junctionless MOSFET (V th <; 0 V) can be made easily. We propose using dual-gate configuration to achieve normally-OFF device for both Ga 2 O 3 planar MOSFET and FinFET. Through TCAD simulations with calibrated parameters, it is found that normally-OFF dual-gate planar device and FinFET can be achieved with 6X and 1X enhancement in ON-current (I ON ), respectively, as higher doping is allowed, while breakdown voltage is not sacrificed.

Junctionless (JL) nanowire is a promising candidate for the future technology nodes because it obviates the need for ultrasteep junction formation. However, with high doping (e.g., 1 x 10(20)cm(-3)) for large on-state current (I-ON) and low contact resistance, it becomes depletion mode (V-TH < 0 V for nMOS and V-TH > 0 V for pMOS). In order to have enhancement-mode device (V-TH > 0 V for nMOS and V-TH < 0 V for pMOS), low doping (e.g., 10(19) cm(-3)) is required, resulting in low current and high contact resistance. We propose two structures to alleviate the problem, which allow very high doping (e.g., 1.5 x 10(20) cm(-3)). The proposed concepts are validated by technology computer aided design simulations using classical and quantum (nonequilibrium Green's function) transport models. The first one is to recess the nanowire under the gate region, resulting in enhancement-mode nMOS with >100% gain in I-ON. The second one is to have a cascode-/dual-gate structure which can further enhance I-ON , reduce I-OFF and increase V-TH with equivalent on-state gate length (L-G) = 5 nm and offstate L-G = 10 nm and 50x increase in ION/IOFF ratio. Such ideas are applicable to other JL devices such as FinFET, silicon-on-insulator, and nanosheets.

TCAD simulation is calibrated to experimental IDVD, IDVG and fT data from an H-terminated diamond MISFET from the literature. With one set of self-consistent parameters, experimental data are all well matched. In the calibration process, TCAD is used to study the possible cause of current degradation in some of the devices fabricated in the same process and it is conjectured that the degradation of low field mobility of the two-dimensional hole gas (2DHG) under the gate is the main cause of current degradation. With the calibrated parameters, a highly scaled MISFET is simulated and it is predicted that with the given fabrication process, one can achieve fT>100GHz if the gate length can be scaled down to ~0.1μm.

Hydrogen-terminated Diamond MESFET exhibits abnormal gate capacitance-voltage (CV) relationship, with an insulator barrier-like plateau followed by an abrupt increase in capacitance at large gate bias. A new model is proposed by assuming inhomogeneous band gap in the Interfacial Layer (IL). With this model, various experimental gate CV, as well as gate leakage curves can be matched well with TCAD simulations. This model also offers possible explanation of the double-bumps in transconductance measurements in some experiments.

A novel normally-off GaN HFET based on layout and stress engineering is proposed and verified using technology CAD (TCAD) simulations. It requires no process modification to existing GaN HFET processes, except that passivation nitride needs to be intrinsically stressed. The device essentially consists of a normally-off low voltage (LV) HFET and a normally-on high voltage (HV) HFET. The LV HFET has a positive pinchoff voltage due to negative piezoelectric charges induced by the patterned nitride. The HV HFET is responsible to sustain most of the drain bias in OFF-state. Drain-induced barrier lowering is suppressed because of the serial configuration. Through TCAD simulations, it is shown that the device is still normally-off at a drain voltage of 1000 V. Device characteristics can be optimized merely through layout and stress engineering. With suitable choice of layout and nitride stress, the electrical performance is similar to a regular normally-on HFET.

A gate stringer normally considered parasitic is used as a subthreshold leakage suppressor in a bulk FinFET. The gate stringer remaining along the source/drain extension suppresses the formation of a sub-fin leakage path and improves the subthreshold slope. The stringer gate structure is implemented by simple process modification in the gate etch step while the other process steps are unchanged. The fabricated stringer gate FinFET shows 35% reduction in the OFF-state leakage current compared with a conventional FinFET without a retrograde well process at the expense of only 5% increase in parasitic capacitance. The power-delay product enhancement at reduced drive voltage characteristics exhibits that the stringer gate FinFET can be an attractive candidate for low standby power and subthreshold logic applications.

We demonstrate that modeling bulk traps and passivation/barrier interface traps in AlGaN/GaN HEMT is necessary to reproduce experimentally observed device behavior. Comparative modeling analysis of different leakage mechanisms in vertical p-n diode with a threading dislocation shows that variable range hopping is the dominant leakage mechanism there. The 3D quantum transport analysis of the impact of threading dislocations on electron mobility for sheet-like and nanowire-like GaN and SiMOSFET channels suggests considerable nanosheet variability and super-sensitive nanowire response. The analysis of voids in electrochemically induced pitting characterizes the impact of different pit types on different key metrics of transistor performance. (c) 2016 The Electrochemical Society. All rights reserved.

Highly degenerated and confined Two-Dimensional Electron Gas (2DEG) is the essential part of AlGaN/GaN HEMTs but is usually modeled classically. We studied the application of Modified Local Density Approximation (MLDA) as a quantum correction to 2DEG in AlGaN/GaN HEMTs. It is found that MLDA is an efficient model that does not degrade the convergence behavior with little run time penalty when the Poisson equation and electron/hole continuity equations are solved self-consistently. It is then applied to a power MISFET and a highly scaled N-polar HEMT for RF applications. It is found that by taking the quantum effect into consideration through MLDA, under certain bias conditions, the drain current can be changed by almost 10% and breakdown voltages are increased substantially. The fT can be changed significantly when gate over-drive is not sufficient.

A novel normally-off AlGaN/GaN HFET (Rake-Gate HFET), based on stress and layout engineering without modifying typical fabrication processes is proposed. It is verified and optimized through TCAD simulation. Positive pinch off voltage is achieved by depositing compressively stressed passivation nitride surrounding gate tines, which induce significant negative piezoelectric charge under the tines. Punch through current is suppressed by including multiple tines connected as in a rake for excellent electrostatic control. It is showed that a properly designed Rake-Gate HFET has > 1000V punch-through and breakdown voltages. It also has smaller gate capacitance than regular HFETs with gates spanning similar areas. By applying the Rake-Gate HFET design to an existing normally-off HFET process (without modifying the fabrication process besides using 500nm -2GPa passivation layer), the pinch off voltage can be further increased by ~1.5V, resulting in the improvement of safe-operating margin and elimination of static energy loss in a 750V single power supply boost converter.

The key factors affecting the efficiency of power electronic systems are the conduction and switching losses in semiconductor power switches. For field-effect transistor switches, the conduction power loss is proportional to the product of the squared current, ION , flowing through the switch in the on-state and the switching loss is proportional to the squared maximum switch voltage, VMAX, the effective device output capacitance, COUT , and the switching frequency, fSW . Therefore, the RONCOUT product is an important figure of merit of a FET-type switch determining the overall power efficiency. Our proposed and implemented Perforated Channel (PC) FET design 1 allowed us to significantly reduce RON , but not COUT. We now propose and demonstrate the improved PC-HFET design that allows us to reduce both RON and COUT . This design reduces the power losses and significantly improves the efficiency of power electronics systems. In the PC-HFET, the portions of the channel under the gate are removed and the remaining channel forms a dash-line of islands WG1 wide with WGG spacing between them. The channel “filling factor” in PC-HFET is kF = WG1/(WG1+WGG ). Compared to conventional HFET with the same total width W, the total channel width and, hence, the device gate capacitance, of the PC-HFET is kF times smaller. However, our analytical estimates, numerical simulations (using the 3D simulation in Synopsys Sentaurus device simulator), and experimental data all show the on-resistance of the PC-HFET can be only 10-15% higher than that of the conventional HFET of the same width. This is achieved due to a strong current spreading effect in the source-to-gate and, especially, in a larger gate-to-drain spacing. The gate capacitance of PC-HFET reduces proportionally to the kF factor as proven by our simulations and experimental data presented in [1]. However our 3D simulations show that the CGD scaling in PC-HFET at high drain voltage is nearly the same as that for conventional HFET. To reduce this capacitance, we proposed the PC-HFET device design with the holes extending into the gate-drain spacing. Our simulations show that the hole extension allows for nearly the same CGD reduction as the gate metal removal over the holes. We used the obtained RON and CGD data to calculate the power loss in AlGaN/GaN PC-HFET and showed that the PC-HFET design filling factor kF = 0.25 reduces the total conversion loss in the power switch by more than a factor of 2. [1] G. Simin, M. Islam, M. Gaevski, J. Deng, R. Gaska, and M. Shur, “Low RC-constant Perforated-Channel HFET”, IEEE El. Dev. Letters, V. 35, pp.449-451, 2014 Figure 1

Using TCAD simulation, we studied the stress effect of pseudomorphically grown Al 0.25 Ga 0.75 N barrier and passivation nitride with intrinsic stress on the electrical characteristics of AlGaN/GaN HEMT. It is found that barrier stress can reduce the two-dimensional electron gas (2DEG) by as much as 15% and change the current by more than 10%, depending on the deformation potential values. Therefore, it is important to extract accurate conduction band deformation potential from experiment or first principle calculation. It is also found that the stress by passivation nitride will induce substantial piezoelectric (PE) charge under the gate region and can be used to adjust the pinch-off voltage through stress engineering for short gate length device.

Variable-range-hopping through dislocations was identified as the main off-state leakage mechanism for GaN vertical diodes on different substrates. The behavior of leakage current for vertical devices as a function of dislocation density and electric field was derived by TCAD simulations, after careful calibration with experiments and literature data. Designed GaN vertical diodes demonstrate 2-4 orders of magnitude lower leakage current while supporting 3-5 times higher electric field, compared to GaN lateral, Si and SiC devices.

Conventional GaN vertical devices, though promising for high-power applications, need expensive GaN substrates. Recently, low-cost GaN-on-Si vertical diodes have been demonstrated for the first time. This paper presents a systematic study to understand and control the OFF-state leakage current in the GaN-on-Si vertical diodes. Various leakage sources were investigated and separated, including leakage through the bulk drift region, passivation layer, etch sidewall, and transition layers. To suppress the leakage along the etch sidewall, an advanced edge termination technology has been developed by combining plasma treatment, tetramethylammonium hydroxide wet etching, and ion implantation. With this advanced edge termination technology, an OFF-state leakage current similar to Si, SiC, and GaN lateral devices has been achieved in the GaN-on-Si vertical diodes with over 300 V breakdown voltage and 2.9-MV/cm peak electric field. The origin of the remaining OFF-state leakage current can be explained by a combination of electron tunneling at the p-GaN/drift-layer interface and carrier hopping between dislocation traps. The low leakage current achieved in these devices demonstrates the great potential of the GaN-on-Si vertical device as a new low-cost candidate for high-performance power electronics.

This paper studies, through Three-Dimensional (3D) TCAD simulations, the formation of gate edge pits on the drain-side of GaN high electron mobility transistors (HEMTs) under electrical stress conditions. These pits are believed to be formed due to electrochemical reactions. The simulations predict that holes, which are necessary to initiate the electrochemical reaction but rare under regular HEMT operating conditions, can be generated through trap-assisted, band-to-band tunneling (B2B TAT). The impact of the electrical behavior of the pit (insulator or metal) on the output characteristics (ID-VD) of the HEMTs were also studied. Insulator-type pits degrade the ON-resistance, RD, while metal-types do not. At medium VD, both types of pit degrade ID, which will be recovered at higher VD. But metal-type requires larger VD to restore the ID. As the pits grow, the hole generation rate first increases (more with metal pit), then decrease after the pit-to-width ratio exceeds 20%.

Numerical simulations to compute stress distributions resulting from stressed overlayers reveal that significant stress fields can penetrate deep into device. Piezoelectric polarization effects from stressed overlayers are only mild due to relatively high stiffness in nitrides but can change band profile along the channel, especially under gate edges. Fringing fields in passivation layers with large dielectric constants can play important role in collapse reduction.

In the last decade, AlGaN/GaN Heterostructure Field Effect Transistors (HFETs) and Metal Oxide Semiconductor HFETs (MOSHFETs) have gained wide recognition as potential devices of choice for ultra high-power microwave systems and power electronics. However, current collapse effects are an important road block for practical applications of these devices and impede realization of their full potential. The elimination of current collapse as well as the ability to predict precise device DC and RF behavior, require understanding of physical phenomena involved. Physicsbased device simulations complementing experimental measurements are the key for gaining qualitative and quantitative insight into the above mentioned phenomena.

We present results from numerical simulations of an AlGaN/GaN heterostructure field effect transistor. Simulations include a polarization model that accounts for non-uniform stress fields and compare results for devices containing uniform and non-uniform stress distributions. Simulations of the electrical characteristics focus on piezoelectric polarization effects. Due to the high stiffness of nitrides, even large stresses in overlayers lead to relatively minor DC and transient electrical effects. Piezoelectric polarization effects are more pronounced for devices with larger AlGaN film strain relaxation.

Over the past decade, the utilization of technology CAD (TCAD) tools has become widespread in industry and academia. The enormous progress in computing hardware and software technology, together with significant advances in physical modelling accuracy, and speed and robustness of numerical algorithms, have made TCAD to a cost-effective albeit powerful technology that complements experimental approaches to wafer processing and metrology.